7184229fea
This Change makes `RegState` into an enum class, with bitwise operators.
It also:
- Updates declarations of flag variables/arguments/returns from
`unsigned` to `RegState`.
- Updates empty RegState initializers from 0 to `{}`.
If this is causing problems in downstream code:
- Adopt the `RegState getXXXRegState(bool)` functions instead of using a
ternary operator such as `bool ? RegState::XXX : 0`.
- Adopt the `bool hasRegState(RegState, RegState)` function instead of
using a bitwise check of the flags.
235 lines
8.4 KiB
C++
235 lines
8.4 KiB
C++
//===-- X86TileConfig.cpp - Tile Register Configure----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Pass to config the shape of AMX physical registers
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/// AMX register need to be configured before use. In X86PreTileConfig pass
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/// the pldtilecfg instruction is inserted, however at that time we don't
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/// know the shape of each physical tile registers, because the register
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/// allocation is not done yet. This pass runs after egister allocation
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/// pass. It collects the shape information of each physical tile register
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/// and store the shape in the stack slot that is allocated for load config
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/// to tile config register.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TileShapeInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-tile-config"
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namespace {
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struct X86TileConfigLegacy : public MachineFunctionPass {
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X86TileConfigLegacy() : MachineFunctionPass(ID) {}
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/// Return the pass name.
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StringRef getPassName() const override { return "Tile Register Configure"; }
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/// X86TileConfig analysis usage.
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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AU.addRequired<VirtRegMapWrapperLegacy>();
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AU.addRequired<LiveIntervalsWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// Perform register allocation.
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().setNoPHIs();
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}
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static char ID;
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};
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} // end anonymous namespace
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char X86TileConfigLegacy::ID = 0;
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INITIALIZE_PASS_BEGIN(X86TileConfigLegacy, DEBUG_TYPE,
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"Tile Register Configure", false, false)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
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INITIALIZE_PASS_END(X86TileConfigLegacy, DEBUG_TYPE, "Tile Register Configure",
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false, false)
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static bool tileConfig(MachineFunction &MF,
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llvm::function_ref<LiveIntervals *()> GetLIs,
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llvm::function_ref<VirtRegMap *()> GetVRM) {
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X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
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// Early exit in the common case of non-AMX code.
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if (X86FI->getAMXProgModel() != AMXProgModelEnum::ManagedRA)
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return false;
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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const X86RegisterInfo *TRI = ST.getRegisterInfo();
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const TargetInstrInfo *TII = ST.getInstrInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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LiveIntervals &LIS = *GetLIs();
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VirtRegMap &VRM = *GetVRM();
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if (VRM.isShapeMapEmpty())
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return false;
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int SS = INT_MAX;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (MI.getOpcode() == X86::PLDTILECFGV) {
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SS = MI.getOperand(0).getIndex();
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break;
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}
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}
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if (SS != INT_MAX)
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break;
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}
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// Didn't find PLDTILECFGV, just return false;
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if (SS == INT_MAX)
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return false;
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// Try to find a point to insert MIs for constant shapes.
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// Here we are leveraging the palette id inserted in PreRA pass.
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unsigned ConstPos = 0;
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MachineInstr *ConstMI = nullptr;
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for (MachineInstr &MI : MF.front()) {
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if (MI.getOpcode() == X86::MOV8mi && SS == MI.getOperand(0).getIndex()) {
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ConstMI = &MI;
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break;
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}
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++ConstPos;
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}
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assert(ConstMI && "Cannot find an insertion point");
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unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs();
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SmallVector<Register, 8> Phys2Virt(AMXRegNum, 0);
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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Register VirtReg = Register::index2VirtReg(I);
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if (MRI.reg_nodbg_empty(VirtReg))
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continue;
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if (!TRI->isTileRegisterClass(MRI.getRegClass(VirtReg)))
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continue;
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MCRegister PhysReg = VRM.getPhys(VirtReg);
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if (!PhysReg)
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continue;
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unsigned Index = PhysReg - X86::TMM0;
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if (!Phys2Virt[Index])
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Phys2Virt[Index] = VirtReg;
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}
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// Fill in the shape of each tile physical register.
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for (unsigned I = 0; I < AMXRegNum; ++I) {
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if (!Phys2Virt[I])
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continue;
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DebugLoc DL;
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bool IsRow = true;
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MachineInstr *NewMI = nullptr;
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ShapeT Shape = VRM.getShape(Phys2Virt[I]);
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for (auto &R : {Shape.getRow()->getReg(), Shape.getCol()->getReg()}) {
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// Here is the data format for the tile config.
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// 0 palette
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// 1 start_row
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// 2-15 reserved, must be zero
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// 16-17 tile0.colsb Tile 0 bytes per row.
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// 18-19 tile1.colsb Tile 1 bytes per row.
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// 20-21 tile2.colsb Tile 2 bytes per row.
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// ... (sequence continues)
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// 30-31 tile7.colsb Tile 7 bytes per row.
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// 32-47 reserved, must be zero
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// 48 tile0.rows Tile 0 rows.
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// 49 tile1.rows Tile 1 rows.
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// 50 tile2.rows Tile 2 rows.
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// ... (sequence continues)
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// 55 tile7.rows Tile 7 rows.
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// 56-63 reserved, must be zero
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int64_t Imm = INT64_MAX;
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int Offset = IsRow ? 48 + I : 16 + I * 2;
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for (auto &DefMI : MRI.def_instructions(R)) {
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MachineBasicBlock &MBB = *DefMI.getParent();
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if (DefMI.isMoveImmediate()) {
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if (Imm != INT64_MAX) {
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// FIXME: We should handle this case in future.
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assert(Imm == DefMI.getOperand(1).getImm() &&
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"Cannot initialize with different shapes");
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continue;
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}
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if (DefMI.getOperand(1).isImm()) {
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Imm = DefMI.getOperand(1).getImm();
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} else {
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assert(DefMI.getOpcode() == X86::MOV32r0 &&
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"The opcode is assumed to be MOV32r0 if the operand is not "
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"immediate.");
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Imm = 0;
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}
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NewMI = addFrameReference(
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BuildMI(MF.front(), ++ConstMI->getIterator(), DL,
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TII->get(IsRow ? X86::MOV8mi : X86::MOV16mi)),
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SS, Offset)
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.addImm(Imm);
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ConstMI = NewMI;
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LIS.InsertMachineInstrInMaps(*NewMI);
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} else {
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unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit;
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unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));
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if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16))
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SubIdx = 0;
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auto Iter = DefMI.getIterator();
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if (&MBB == &MF.front() &&
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(unsigned)std::distance(MBB.instr_begin(), Iter) < ConstPos)
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Iter = ConstMI->getIterator();
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NewMI = addFrameReference(
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BuildMI(MBB, ++Iter, DL,
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TII->get(IsRow ? X86::MOV8mr : X86::MOV16mr)),
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SS, Offset)
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.addReg(R, {}, SubIdx);
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SlotIndex SIdx = LIS.InsertMachineInstrInMaps(*NewMI);
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LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});
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}
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}
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IsRow = false;
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}
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}
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return true;
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}
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FunctionPass *llvm::createX86TileConfigLegacyPass() {
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return new X86TileConfigLegacy();
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}
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bool X86TileConfigLegacy::runOnMachineFunction(MachineFunction &MF) {
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return tileConfig(
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MF,
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[this]() { return &getAnalysis<LiveIntervalsWrapperPass>().getLIS(); },
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[this]() { return &getAnalysis<VirtRegMapWrapperLegacy>().getVRM(); });
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}
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PreservedAnalyses X86TileConfigPass::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM) {
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bool Changed = tileConfig(
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MF, [&MFAM, &MF]() { return &MFAM.getResult<LiveIntervalsAnalysis>(MF); },
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[&MFAM, &MF]() { return &MFAM.getResult<VirtRegMapAnalysis>(MF); });
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return Changed ? getMachineFunctionPassPreservedAnalyses()
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.preserveSet<CFGAnalyses>()
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: PreservedAnalyses::all();
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}
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