1034bb57ae
There is no easy way to materialise some fixed-width vector constants with 64-bit elements. This is because NEON's movi instruction is restricted to setting all bits in a byte to the same value, i.e. 0xFF can be encoded as an immediate but not 0x1F. However, if SVE is available we can use the dup instruction to cover more cases. Rather than lower the immediate directly using the dup instruction, I've instead used the generic SPLAT_VECTOR node in combination with an EXTRACT_SUBVECTOR. This is because we already have SVE splat_vector patterns that can match directly to dup.
222 lines
7.1 KiB
LLVM
222 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mattr=+sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define i1 @extract_icmp_v4i32_const_splat_rhs(<4 x i32> %a) {
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; CHECK-LABEL: extract_icmp_v4i32_const_splat_rhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: cmp w8, #5
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%icmp = icmp ult <4 x i32> %a, splat (i32 5)
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%ext = extractelement <4 x i1> %icmp, i32 1
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ret i1 %ext
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}
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define i1 @extract_icmp_v4i32_const_splat_lhs(<4 x i32> %a) {
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; CHECK-LABEL: extract_icmp_v4i32_const_splat_lhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: cmp w8, #7
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; CHECK-NEXT: cset w0, hi
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; CHECK-NEXT: ret
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%icmp = icmp ult <4 x i32> splat(i32 7), %a
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%ext = extractelement <4 x i1> %icmp, i32 1
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ret i1 %ext
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}
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define i1 @extract_icmp_v4i32_const_vec_rhs(<4 x i32> %a) {
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; CHECK-LABEL: extract_icmp_v4i32_const_vec_rhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, v0.s[1]
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; CHECK-NEXT: cmp w8, #234
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%icmp = icmp ult <4 x i32> %a, <i32 5, i32 234, i32 -1, i32 7>
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%ext = extractelement <4 x i1> %icmp, i32 1
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ret i1 %ext
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}
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define i1 @extract_fcmp_v4f32_const_splat_rhs(<4 x float> %a) {
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; CHECK-LABEL: extract_fcmp_v4f32_const_splat_rhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov s0, v0.s[1]
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; CHECK-NEXT: fmov s1, #4.00000000
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: ret
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%fcmp = fcmp ult <4 x float> %a, splat(float 4.0e+0)
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%ext = extractelement <4 x i1> %fcmp, i32 1
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ret i1 %ext
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}
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; Tests the code in ExpandIntRes_SETCC
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define i128 @extract_icmp_v1i128(ptr %p) {
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; CHECK-LABEL: extract_icmp_v1i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp x9, x8, [x0]
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; CHECK-NEXT: orr x8, x9, x8
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: sbfx x0, x8, #0, #1
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; CHECK-NEXT: mov x1, x0
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; CHECK-NEXT: ret
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%load = load <1 x i128>, ptr %p, align 16
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%cmp = icmp eq <1 x i128> %load, zeroinitializer
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%sext = sext <1 x i1> %cmp to <1 x i128>
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%res = extractelement <1 x i128> %sext, i32 0
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ret i128 %res
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}
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define void @vector_loop_with_icmp(ptr nocapture noundef writeonly %dest) {
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; CHECK-LABEL: vector_loop_with_icmp:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.d, #0, #1
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; CHECK-NEXT: mov z1.d, #2 // =0x2
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; CHECK-NEXT: add x8, x0, #4
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; CHECK-NEXT: mov w9, #16 // =0x10
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; CHECK-NEXT: mov w10, #1 // =0x1
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; CHECK-NEXT: b .LBB5_2
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; CHECK-NEXT: .LBB5_1: // %pred.store.continue6
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; CHECK-NEXT: // in Loop: Header=BB5_2 Depth=1
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; CHECK-NEXT: add v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: subs x9, x9, #2
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; CHECK-NEXT: add x8, x8, #8
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; CHECK-NEXT: b.eq .LBB5_6
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; CHECK-NEXT: .LBB5_2: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: fmov x11, d0
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; CHECK-NEXT: cmp x11, #14
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; CHECK-NEXT: b.hi .LBB5_4
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; CHECK-NEXT: // %bb.3: // %pred.store.if
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; CHECK-NEXT: // in Loop: Header=BB5_2 Depth=1
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; CHECK-NEXT: stur w10, [x8, #-4]
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; CHECK-NEXT: .LBB5_4: // %pred.store.continue
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; CHECK-NEXT: // in Loop: Header=BB5_2 Depth=1
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; CHECK-NEXT: mov x11, v0.d[1]
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; CHECK-NEXT: cmp x11, #14
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; CHECK-NEXT: b.hi .LBB5_1
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; CHECK-NEXT: // %bb.5: // %pred.store.if5
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; CHECK-NEXT: // in Loop: Header=BB5_2 Depth=1
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; CHECK-NEXT: str w10, [x8]
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; CHECK-NEXT: b .LBB5_1
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; CHECK-NEXT: .LBB5_6: // %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %pred.store.continue6 ]
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%vec.ind = phi <2 x i64> [ <i64 0, i64 1>, %entry ], [ %vec.ind.next, %pred.store.continue6 ]
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%vec.cmp = icmp ult <2 x i64> %vec.ind, <i64 15, i64 15>
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%c0 = extractelement <2 x i1> %vec.cmp, i64 0
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br i1 %c0, label %pred.store.if, label %pred.store.continue
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pred.store.if:
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%arrayidx = getelementptr inbounds i32, ptr %dest, i64 %index
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store i32 1, ptr %arrayidx, align 4
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br label %pred.store.continue
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pred.store.continue:
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%c1 = extractelement <2 x i1> %vec.cmp, i64 1
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br i1 %c1, label %pred.store.if5, label %pred.store.continue6
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pred.store.if5:
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%indexp1 = or disjoint i64 %index, 1
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%arrayidx2 = getelementptr inbounds i32, ptr %dest, i64 %indexp1
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store i32 1, ptr %arrayidx2, align 4
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br label %pred.store.continue6
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pred.store.continue6:
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%index.next = add i64 %index, 2
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%vec.ind.next = add <2 x i64> %vec.ind, <i64 2, i64 2>
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%index.cmp = icmp eq i64 %index.next, 16
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br i1 %index.cmp, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}
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define i32 @issue_121372(<4 x i32> %v) {
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; CHECK-LABEL: issue_121372:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: csetm w8, eq
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: csetm w0, lt
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; CHECK-NEXT: ret
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%cmp_ule = icmp ule <4 x i32> %v, zeroinitializer
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%sext_v4i1 = sext <4 x i1> %cmp_ule to <4 x i32>
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%cmp_sge = icmp sge <4 x i32> zeroinitializer, %sext_v4i1
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%ext = extractelement <4 x i1> %cmp_sge, i32 0
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%res = sext i1 %ext to i32
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ret i32 %res
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}
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; Negative tests
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define i1 @extract_icmp_v4i32_splat_rhs(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: extract_icmp_v4i32_splat_rhs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup v1.4s, w0
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; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: umov w8, v0.h[1]
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%ins = insertelement <4 x i32> poison, i32 %b, i32 0
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%splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer
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%icmp = icmp ult <4 x i32> %a, %splat
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%ext = extractelement <4 x i1> %icmp, i32 1
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ret i1 %ext
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}
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define i1 @extract_icmp_v4i32_splat_rhs_mul_use(<4 x i32> %a, ptr %p) {
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; CHECK-LABEL: extract_icmp_v4i32_splat_rhs_mul_use:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #235
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; CHECK-NEXT: adrp x8, .LCPI8_0
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
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; CHECK-NEXT: mov x8, x0
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; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v1.4h, v0.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: umov w9, v1.h[1]
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; CHECK-NEXT: str b0, [x8]
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; CHECK-NEXT: and w0, w9, #0x1
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; CHECK-NEXT: ret
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%icmp = icmp ult <4 x i32> %a, splat(i32 235)
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%ext = extractelement <4 x i1> %icmp, i32 1
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store <4 x i1> %icmp, ptr %p, align 4
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ret i1 %ext
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}
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define i1 @extract_icmp_v4i32_splat_rhs_unknown_idx(<4 x i32> %a, i32 %c) {
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; CHECK-LABEL: extract_icmp_v4i32_splat_rhs_unknown_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: movi v1.4s, #127
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; CHECK-NEXT: add x8, sp, #8
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: bfi x8, x0, #1, #2
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; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: ldrh w8, [x8]
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%icmp = icmp ult <4 x i32> %a, splat(i32 127)
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%ext = extractelement <4 x i1> %icmp, i32 %c
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ret i1 %ext
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}
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