d748c81218
The 16-bit immediate operand of s_waitcnt_depctr / s_wait_alu has some unused bits. Previously codegen would set these bits to 1, but setting them to 0 matches the SP3 assembler behaviour better, which in turn means that we can print them using the human readable SP3 syntax: s_wait_alu 0xfffd ; unused bits set to 1 s_wait_alu 0xff9d ; unused bits set to 0 s_wait_alu depctr_va_vcc(0) ; unused bits set to 0, human readable Note that the set of unused bits changed between GFX10.1 and GFX10.3.
70 lines
2.6 KiB
LLVM
70 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
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define amdgpu_kernel void @entry_fn() {
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; CHECK-LABEL: entry_fn:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_sext_i32_i16 s5, s5
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; CHECK-NEXT: s_add_co_u32 s4, s4, entry_fn@gotpcrel32@lo+8
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; CHECK-NEXT: s_add_co_ci_u32 s5, s5, entry_fn@gotpcrel32@hi+16
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
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; CHECK-NEXT: s_wait_kmcnt 0x0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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entry:
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call void @entry_fn()
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ret void
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}
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define void @caller() {
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; CHECK-LABEL: caller:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
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; CHECK-NEXT: s_wait_expcnt 0x0
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; CHECK-NEXT: s_wait_samplecnt 0x0
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; CHECK-NEXT: s_wait_bvhcnt 0x0
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; CHECK-NEXT: s_wait_kmcnt 0x0
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; CHECK-NEXT: s_mov_b32 s0, s33
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; CHECK-NEXT: s_mov_b32 s33, s32
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; CHECK-NEXT: s_or_saveexec_b32 s1, -1
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; CHECK-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill
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; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
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; CHECK-NEXT: s_mov_b32 exec_lo, s1
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; CHECK-NEXT: s_add_co_i32 s32, s32, 16
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; CHECK-NEXT: v_writelane_b32 v40, s0, 2
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; CHECK-NEXT: s_mov_b64 s[0:1], s[4:5]
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
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; CHECK-NEXT: s_sext_i32_i16 s5, s5
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; CHECK-NEXT: s_add_co_u32 s4, s4, entry_fn@gotpcrel32@lo+12
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; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
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; CHECK-NEXT: s_add_co_ci_u32 s5, s5, entry_fn@gotpcrel32@hi+24
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; CHECK-NEXT: v_mov_b32_e32 v0, v31
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; CHECK-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
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; CHECK-NEXT: v_writelane_b32 v40, s30, 0
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; CHECK-NEXT: s_mov_b64 s[2:3], s[6:7]
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; CHECK-NEXT: s_mov_b64 s[6:7], s[10:11]
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; CHECK-NEXT: v_writelane_b32 v40, s31, 1
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; CHECK-NEXT: s_wait_kmcnt 0x0
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; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_readlane_b32 s31, v40, 1
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; CHECK-NEXT: v_readlane_b32 s30, v40, 0
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; CHECK-NEXT: s_mov_b32 s32, s33
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; CHECK-NEXT: v_readlane_b32 s0, v40, 2
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; CHECK-NEXT: s_or_saveexec_b32 s1, -1
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; CHECK-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload
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; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
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; CHECK-NEXT: s_mov_b32 exec_lo, s1
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; CHECK-NEXT: s_mov_b32 s33, s0
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; CHECK-NEXT: s_wait_loadcnt 0x0
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; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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call void @entry_fn()
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ret void
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}
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