288 lines
9.1 KiB
YAML
288 lines
9.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @float_add() {entry: ret void}
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define void @float_sub() {entry: ret void}
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define void @float_mul() {entry: ret void}
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define void @float_div() {entry: ret void}
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define void @double_add() {entry: ret void}
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define void @double_sub() {entry: ret void}
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define void @double_mul() {entry: ret void}
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define void @double_div() {entry: ret void}
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...
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---
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name: float_add
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_add
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; FP32: liveins: $f12, $f14
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32-NEXT: [[FADD_S:%[0-9]+]]:fgr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $f0 = COPY [[FADD_S]]
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; FP32-NEXT: RetRA implicit $f0
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;
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; FP64-LABEL: name: float_add
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; FP64: liveins: $f12, $f14
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64-NEXT: [[FADD_S:%[0-9]+]]:fgr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $f0 = COPY [[FADD_S]]
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; FP64-NEXT: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FADD %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_sub
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_sub
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; FP32: liveins: $f12, $f14
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32-NEXT: [[FSUB_S:%[0-9]+]]:fgr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $f0 = COPY [[FSUB_S]]
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; FP32-NEXT: RetRA implicit $f0
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;
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; FP64-LABEL: name: float_sub
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; FP64: liveins: $f12, $f14
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64-NEXT: [[FSUB_S:%[0-9]+]]:fgr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $f0 = COPY [[FSUB_S]]
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; FP64-NEXT: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FSUB %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_mul
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_mul
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; FP32: liveins: $f12, $f14
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32-NEXT: [[FMUL_S:%[0-9]+]]:fgr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $f0 = COPY [[FMUL_S]]
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; FP32-NEXT: RetRA implicit $f0
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;
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; FP64-LABEL: name: float_mul
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; FP64: liveins: $f12, $f14
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64-NEXT: [[FMUL_S:%[0-9]+]]:fgr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $f0 = COPY [[FMUL_S]]
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; FP64-NEXT: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FMUL %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: float_div
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12, $f14
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; FP32-LABEL: name: float_div
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; FP32: liveins: $f12, $f14
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP32-NEXT: [[FDIV_S:%[0-9]+]]:fgr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $f0 = COPY [[FDIV_S]]
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; FP32-NEXT: RetRA implicit $f0
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;
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; FP64-LABEL: name: float_div
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; FP64: liveins: $f12, $f14
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
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; FP64-NEXT: [[FDIV_S:%[0-9]+]]:fgr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $f0 = COPY [[FDIV_S]]
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; FP64-NEXT: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = COPY $f14
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%2:fprb(s32) = G_FDIV %0, %1
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: double_add
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_add
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; FP32: liveins: $d6, $d7
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32-NEXT: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32-NEXT: [[FADD_D32_:%[0-9]+]]:afgr64 = nofpexcept FADD_D32 [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $d0 = COPY [[FADD_D32_]]
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; FP32-NEXT: RetRA implicit $d0
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;
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; FP64-LABEL: name: double_add
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; FP64: liveins: $d6, $d7
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64-NEXT: [[FADD_D64_:%[0-9]+]]:fgr64 = nofpexcept FADD_D64 [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $d0 = COPY [[FADD_D64_]]
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; FP64-NEXT: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FADD %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: double_sub
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_sub
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; FP32: liveins: $d6, $d7
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32-NEXT: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32-NEXT: [[FSUB_D32_:%[0-9]+]]:afgr64 = nofpexcept FSUB_D32 [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $d0 = COPY [[FSUB_D32_]]
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; FP32-NEXT: RetRA implicit $d0
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;
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; FP64-LABEL: name: double_sub
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; FP64: liveins: $d6, $d7
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64-NEXT: [[FSUB_D64_:%[0-9]+]]:fgr64 = nofpexcept FSUB_D64 [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $d0 = COPY [[FSUB_D64_]]
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; FP64-NEXT: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FSUB %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: double_mul
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_mul
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; FP32: liveins: $d6, $d7
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32-NEXT: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32-NEXT: [[FMUL_D32_:%[0-9]+]]:afgr64 = nofpexcept FMUL_D32 [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $d0 = COPY [[FMUL_D32_]]
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; FP32-NEXT: RetRA implicit $d0
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;
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; FP64-LABEL: name: double_mul
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; FP64: liveins: $d6, $d7
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64-NEXT: [[FMUL_D64_:%[0-9]+]]:fgr64 = nofpexcept FMUL_D64 [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $d0 = COPY [[FMUL_D64_]]
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; FP64-NEXT: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FMUL %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: double_div
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6, $d7
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; FP32-LABEL: name: double_div
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; FP32: liveins: $d6, $d7
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; FP32-NEXT: {{ $}}
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; FP32-NEXT: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32-NEXT: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
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; FP32-NEXT: [[FDIV_D32_:%[0-9]+]]:afgr64 = nofpexcept FDIV_D32 [[COPY]], [[COPY1]], implicit $fcr31
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; FP32-NEXT: $d0 = COPY [[FDIV_D32_]]
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; FP32-NEXT: RetRA implicit $d0
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;
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; FP64-LABEL: name: double_div
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; FP64: liveins: $d6, $d7
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; FP64-NEXT: {{ $}}
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; FP64-NEXT: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64-NEXT: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
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; FP64-NEXT: [[FDIV_D64_:%[0-9]+]]:fgr64 = nofpexcept FDIV_D64 [[COPY]], [[COPY1]], implicit $fcr31
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; FP64-NEXT: $d0 = COPY [[FDIV_D64_]]
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; FP64-NEXT: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = COPY $d7
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%2:fprb(s64) = G_FDIV %0, %1
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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