743f0a4fdb
This patch is for special cases involving 0 vectors. During the comparison of vector operands, current code generation checks with `vcmpequh (vector compare equal unsigned halfword)` followed by a negation `xxlnor (VSX Vector Logical NOR XX3-form)`. This means that for the special case, instead of using `vcmpequh` and then negating the result, we can directly use `vcmpgtuh (vector compare greater than unsigned halfword)`. As a result the negation is avoided since the only condition where this will be false is for 0 as it is an `unsigned halfword`. --------- Co-authored-by: himadhith <himadhith.v@ibm.com>
171 lines
6.5 KiB
LLVM
171 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32
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define i32 @test_Greater_than(ptr %colauths) {
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; This testcase is for the special case of zero-vector comparisons.
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; Optimize zero-vector `vcmpequh` compares followed by negate to `vcmpgtuh`.
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; POWERPC_64LE-LABEL: test_Greater_than:
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; POWERPC_64LE: # %bb.0: # %entry
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; POWERPC_64LE-NEXT: lfd f0, 0(r3)
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; POWERPC_64LE-NEXT: xxlxor v3, v3, v3
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; POWERPC_64LE-NEXT: li r4, 0
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; POWERPC_64LE-NEXT: li r3, 4
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; POWERPC_64LE-NEXT: xxswapd v2, f0
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; POWERPC_64LE-NEXT: vcmpgtuh v2, v2, v3
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; POWERPC_64LE-NEXT: vmrglh v3, v2, v2
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; POWERPC_64LE-NEXT: vextuwrx r4, r4, v2
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; POWERPC_64LE-NEXT: vextuwrx r3, r3, v3
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; POWERPC_64LE-NEXT: clrlwi r4, r4, 31
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; POWERPC_64LE-NEXT: rlwimi r4, r3, 1, 30, 30
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; POWERPC_64LE-NEXT: mfvsrwz r3, v3
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; POWERPC_64LE-NEXT: rlwimi r4, r3, 2, 29, 29
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; POWERPC_64LE-NEXT: li r3, 12
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; POWERPC_64LE-NEXT: vextuwrx r3, r3, v3
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; POWERPC_64LE-NEXT: rlwimi r4, r3, 3, 28, 28
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; POWERPC_64LE-NEXT: stb r4, -1(r1)
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; POWERPC_64LE-NEXT: lbz r3, -1(r1)
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; POWERPC_64LE-NEXT: popcntd r3, r3
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; POWERPC_64LE-NEXT: blr
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;
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; POWERPC_64-LABEL: test_Greater_than:
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; POWERPC_64: # %bb.0: # %entry
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; POWERPC_64-NEXT: lxsd v2, 0(r3)
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; POWERPC_64-NEXT: xxlxor v3, v3, v3
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; POWERPC_64-NEXT: li r4, 12
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; POWERPC_64-NEXT: li r3, 8
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; POWERPC_64-NEXT: vcmpgtuh v2, v2, v3
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; POWERPC_64-NEXT: vmrghh v2, v2, v2
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; POWERPC_64-NEXT: vextuwlx r4, r4, v2
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; POWERPC_64-NEXT: vextuwlx r3, r3, v2
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; POWERPC_64-NEXT: clrlwi r4, r4, 31
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; POWERPC_64-NEXT: rlwimi r4, r3, 1, 30, 30
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; POWERPC_64-NEXT: mfvsrwz r3, v2
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; POWERPC_64-NEXT: rlwimi r4, r3, 2, 29, 29
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; POWERPC_64-NEXT: li r3, 0
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; POWERPC_64-NEXT: vextuwlx r3, r3, v2
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; POWERPC_64-NEXT: rlwimi r4, r3, 3, 28, 28
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; POWERPC_64-NEXT: stb r4, -1(r1)
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; POWERPC_64-NEXT: lbz r3, -1(r1)
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; POWERPC_64-NEXT: popcntd r3, r3
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; POWERPC_64-NEXT: blr
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;
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; POWERPC_32-LABEL: test_Greater_than:
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; POWERPC_32: # %bb.0: # %entry
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; POWERPC_32-NEXT: li r4, 4
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; POWERPC_32-NEXT: lxvwsx vs1, 0, r3
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; POWERPC_32-NEXT: xxlxor v3, v3, v3
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; POWERPC_32-NEXT: lxvwsx vs0, r3, r4
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; POWERPC_32-NEXT: xxmrghw v2, vs1, vs0
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; POWERPC_32-NEXT: vcmpgtuh v2, v2, v3
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; POWERPC_32-NEXT: vmrghh v2, v2, v2
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; POWERPC_32-NEXT: stxv v2, -32(r1)
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; POWERPC_32-NEXT: lwz r3, -20(r1)
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; POWERPC_32-NEXT: lwz r4, -24(r1)
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; POWERPC_32-NEXT: clrlwi r3, r3, 31
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; POWERPC_32-NEXT: rlwimi r3, r4, 1, 30, 30
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; POWERPC_32-NEXT: lwz r4, -28(r1)
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; POWERPC_32-NEXT: rlwimi r3, r4, 2, 29, 29
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; POWERPC_32-NEXT: lwz r4, -32(r1)
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; POWERPC_32-NEXT: rlwimi r3, r4, 3, 28, 28
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; POWERPC_32-NEXT: popcntw r3, r3
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; POWERPC_32-NEXT: blr
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entry:
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%0 = load <4 x i16>, ptr %colauths, align 2, !tbaa !5
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%1 = icmp ne <4 x i16> %0, zeroinitializer
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%2 = bitcast <4 x i1> %1 to i4
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%3 = tail call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 %2)
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%4 = zext nneg i4 %3 to i32
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ret i32 %4
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}
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declare i4 @llvm.ctpop.i4(i4) #1
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!5 = !{!6, !6, i64 0}
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!6 = !{!"short", !7, i64 0}
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!7 = !{!"omnipotent char", !8, i64 0}
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!8 = !{!"Simple C/C++ TBAA"}
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; Function to lockdown changes for floating point vector comparisons
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define range(i32 0, 5) i32 @cols_needed(ptr %colauths){
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; POWERPC_64LE-LABEL: cols_needed:
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; POWERPC_64LE: # %bb.0: # %entry
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; POWERPC_64LE-NEXT: lxv vs0, 0(r3)
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; POWERPC_64LE-NEXT: xxlxor vs1, vs1, vs1
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; POWERPC_64LE-NEXT: li r4, 4
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; POWERPC_64LE-NEXT: li r3, 0
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; POWERPC_64LE-NEXT: xvcmpeqsp vs0, vs0, vs1
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; POWERPC_64LE-NEXT: xxlnor v2, vs0, vs0
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; POWERPC_64LE-NEXT: vextuwrx r4, r4, v2
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; POWERPC_64LE-NEXT: vextuwrx r3, r3, v2
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; POWERPC_64LE-NEXT: rlwinm r4, r4, 1, 30, 30
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; POWERPC_64LE-NEXT: sub r3, r4, r3
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; POWERPC_64LE-NEXT: mfvsrwz r4, v2
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; POWERPC_64LE-NEXT: rlwinm r4, r4, 2, 29, 29
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; POWERPC_64LE-NEXT: or r3, r3, r4
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; POWERPC_64LE-NEXT: li r4, 12
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; POWERPC_64LE-NEXT: vextuwrx r4, r4, v2
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; POWERPC_64LE-NEXT: slwi r4, r4, 3
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; POWERPC_64LE-NEXT: or r3, r3, r4
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; POWERPC_64LE-NEXT: clrlwi r3, r3, 28
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; POWERPC_64LE-NEXT: stb r3, -1(r1)
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; POWERPC_64LE-NEXT: lbz r3, -1(r1)
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; POWERPC_64LE-NEXT: popcntd r3, r3
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; POWERPC_64LE-NEXT: blr
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;
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; POWERPC_64-LABEL: cols_needed:
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; POWERPC_64: # %bb.0: # %entry
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; POWERPC_64-NEXT: lxv vs0, 0(r3)
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; POWERPC_64-NEXT: xxlxor vs1, vs1, vs1
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; POWERPC_64-NEXT: li r4, 8
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; POWERPC_64-NEXT: xvcmpeqsp vs0, vs0, vs1
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; POWERPC_64-NEXT: xxlnor v2, vs0, vs0
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; POWERPC_64-NEXT: vextuwlx r4, r4, v2
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; POWERPC_64-NEXT: mfvsrwz r3, v2
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; POWERPC_64-NEXT: rlwinm r4, r4, 1, 30, 30
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; POWERPC_64-NEXT: rlwimi r4, r3, 2, 29, 29
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; POWERPC_64-NEXT: li r3, 0
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; POWERPC_64-NEXT: vextuwlx r3, r3, v2
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; POWERPC_64-NEXT: rlwimi r4, r3, 3, 0, 28
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; POWERPC_64-NEXT: li r3, 12
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; POWERPC_64-NEXT: vextuwlx r3, r3, v2
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; POWERPC_64-NEXT: sub r3, r4, r3
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; POWERPC_64-NEXT: clrlwi r3, r3, 28
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; POWERPC_64-NEXT: stb r3, -1(r1)
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; POWERPC_64-NEXT: lbz r3, -1(r1)
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; POWERPC_64-NEXT: popcntd r3, r3
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; POWERPC_64-NEXT: blr
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;
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; POWERPC_32-LABEL: cols_needed:
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; POWERPC_32: # %bb.0: # %entry
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; POWERPC_32-NEXT: lxv vs0, 0(r3)
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; POWERPC_32-NEXT: xxlxor vs1, vs1, vs1
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; POWERPC_32-NEXT: xvcmpeqsp vs0, vs0, vs1
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; POWERPC_32-NEXT: xxlnor vs0, vs0, vs0
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; POWERPC_32-NEXT: stxv vs0, -32(r1)
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; POWERPC_32-NEXT: lwz r3, -24(r1)
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; POWERPC_32-NEXT: lwz r4, -28(r1)
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; POWERPC_32-NEXT: rlwinm r3, r3, 1, 30, 30
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; POWERPC_32-NEXT: rlwimi r3, r4, 2, 29, 29
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; POWERPC_32-NEXT: lwz r4, -32(r1)
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; POWERPC_32-NEXT: rlwimi r3, r4, 3, 0, 28
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; POWERPC_32-NEXT: lwz r4, -20(r1)
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; POWERPC_32-NEXT: sub r3, r3, r4
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; POWERPC_32-NEXT: clrlwi r3, r3, 28
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; POWERPC_32-NEXT: popcntw r3, r3
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; POWERPC_32-NEXT: blr
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entry:
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%0 = load <4 x float>, ptr %colauths, align 4, !tbaa !5
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%1 = fcmp une <4 x float> %0, zeroinitializer
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%2 = bitcast <4 x i1> %1 to i4
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%3 = tail call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 %2)
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%4 = zext nneg i4 %3 to i32
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ret i32 %4
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}
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