c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
123 lines
3.8 KiB
LLVM
123 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s --check-prefix=VECTOR
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;
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; Test insertions into fp16 vectors.
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define <8 x half> @f0(half %val) {
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; CHECK-LABEL: f0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
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; CHECK-NEXT: lgdr %r0, %f0
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 4(%r2)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f0:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: # kill: def $f0h killed $f0h def $v0
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; VECTOR-NEXT: vreph %v24, %v0, 0
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; VECTOR-NEXT: br %r14
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%ret = insertelement <8 x half> poison, half %val, i32 2
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ret <8 x half> %ret
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}
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define <8 x half> @f1(half %val) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
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; CHECK-NEXT: lgdr %r0, %f0
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 6(%r2)
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; CHECK-NEXT: sth %r0, 4(%r2)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f1:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: # kill: def $f0h killed $f0h def $v0
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; VECTOR-NEXT: vreph %v24, %v0, 0
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; VECTOR-NEXT: br %r14
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%v0 = insertelement <8 x half> poison, half %val, i32 2
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%ret = insertelement <8 x half> %v0, half %val, i32 3
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ret <8 x half> %ret
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}
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define <8 x half> @f2(half %val0, half %val1) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $f2h killed $f2h def $f2d
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; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
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; CHECK-NEXT: lgdr %r0, %f2
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 6(%r2)
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; CHECK-NEXT: lgdr %r0, %f0
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 4(%r2)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f2:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: # kill: def $f2h killed $f2h def $v2
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; VECTOR-NEXT: # kill: def $f0h killed $f0h def $v0
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; VECTOR-NEXT: vmrhh %v0, %v0, %v2
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; VECTOR-NEXT: vmrhf %v0, %v0, %v0
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; VECTOR-NEXT: vmrhg %v24, %v0, %v0
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; VECTOR-NEXT: br %r14
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%v0 = insertelement <8 x half> poison, half %val0, i32 2
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%ret = insertelement <8 x half> %v0, half %val1, i32 3
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ret <8 x half> %ret
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}
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define <8 x half> @f3(half %val0, half %val1) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $f2h killed $f2h def $f2d
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; CHECK-NEXT: # kill: def $f0h killed $f0h def $f0d
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; CHECK-NEXT: lgdr %r0, %f2
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; CHECK-NEXT: srlg %r0, %r0, 48
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; CHECK-NEXT: sth %r0, 10(%r2)
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; CHECK-NEXT: lgdr %r1, %f0
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; CHECK-NEXT: srlg %r1, %r1, 48
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; CHECK-NEXT: sth %r1, 8(%r2)
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; CHECK-NEXT: sth %r0, 6(%r2)
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; CHECK-NEXT: sth %r1, 4(%r2)
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f3:
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; VECTOR: # %bb.0:
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; VECTOR-NEXT: # kill: def $f2h killed $f2h def $v2
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; VECTOR-NEXT: # kill: def $f0h killed $f0h def $v0
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; VECTOR-NEXT: vmrhh %v0, %v0, %v2
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; VECTOR-NEXT: vmrhf %v0, %v0, %v0
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; VECTOR-NEXT: vmrhg %v24, %v0, %v0
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; VECTOR-NEXT: br %r14
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%v0 = insertelement <8 x half> poison, half %val0, i32 2
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%v1 = insertelement <8 x half> %v0, half %val1, i32 3
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%v2 = insertelement <8 x half> %v1, half %val0, i32 4
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%ret = insertelement <8 x half> %v2, half %val1, i32 5
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ret <8 x half> %ret
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}
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; Test creation of vregs where the arg gets one VR128 which is split into two
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; VR16 parts.
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define <2 x half> @f4(<2 x half> %0) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lzer %f0
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; CHECK-NEXT: br %r14
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;
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; VECTOR-LABEL: f4:
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; VECTOR: # %bb.0: # %entry
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; VECTOR-NEXT: vreph %v0, %v24, 1
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; VECTOR-NEXT: vuplhh %v0, %v0
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; VECTOR-NEXT: vmrhf %v0, %v0, %v0
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; VECTOR-NEXT: vmrhg %v24, %v0, %v0
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; VECTOR-NEXT: br %r14
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entry:
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br label %body
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body: ; preds = %entry
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%2 = insertelement <2 x half> %0, half 0x0000, i64 0
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ret <2 x half> %2
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}
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