c999e9a4fe
- Make v8f16 a legal type so that arguments can be passed in vector registers. Handle fp16 vectors so that they have the same ABI as other fp vectors. - Set the preferred vector action for fp16 vectors to "split". This will scalarize all operations, which is not always necessary (like with memory operations), but it avoids the superfluous operations that result after first widening and then scalarizing a narrow vector (like v4f16). Fixes #168992
213 lines
6.1 KiB
LLVM
213 lines
6.1 KiB
LLVM
; Test vector insertion of register variables.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v16i8 insertion into the first element.
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define <16 x i8> @f1(<16 x i8> %val, i8 %element) {
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; CHECK-LABEL: f1:
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; CHECK: vlvgb %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <16 x i8> %val, i8 %element, i32 0
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ret <16 x i8> %ret
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}
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; Test v16i8 insertion into the last element.
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define <16 x i8> @f2(<16 x i8> %val, i8 %element) {
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; CHECK-LABEL: f2:
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; CHECK: vlvgb %v24, %r2, 15
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; CHECK: br %r14
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%ret = insertelement <16 x i8> %val, i8 %element, i32 15
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ret <16 x i8> %ret
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}
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; Test v16i8 insertion into a variable element.
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define <16 x i8> @f3(<16 x i8> %val, i8 %element, i32 %index) {
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; CHECK-LABEL: f3:
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; CHECK: vlvgb %v24, %r2, 0(%r3)
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; CHECK: br %r14
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%ret = insertelement <16 x i8> %val, i8 %element, i32 %index
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ret <16 x i8> %ret
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}
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; Test v8i16 insertion into the first element.
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define <8 x i16> @f4(<8 x i16> %val, i16 %element) {
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; CHECK-LABEL: f4:
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; CHECK: vlvgh %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <8 x i16> %val, i16 %element, i32 0
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ret <8 x i16> %ret
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}
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; Test v8i16 insertion into the last element.
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define <8 x i16> @f5(<8 x i16> %val, i16 %element) {
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; CHECK-LABEL: f5:
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; CHECK: vlvgh %v24, %r2, 7
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; CHECK: br %r14
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%ret = insertelement <8 x i16> %val, i16 %element, i32 7
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ret <8 x i16> %ret
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}
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; Test v8i16 insertion into a variable element.
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define <8 x i16> @f6(<8 x i16> %val, i16 %element, i32 %index) {
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; CHECK-LABEL: f6:
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; CHECK: vlvgh %v24, %r2, 0(%r3)
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; CHECK: br %r14
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%ret = insertelement <8 x i16> %val, i16 %element, i32 %index
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ret <8 x i16> %ret
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}
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; Test v4i32 insertion into the first element.
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define <4 x i32> @f7(<4 x i32> %val, i32 %element) {
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; CHECK-LABEL: f7:
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; CHECK: vlvgf %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <4 x i32> %val, i32 %element, i32 0
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ret <4 x i32> %ret
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}
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; Test v4i32 insertion into the last element.
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define <4 x i32> @f8(<4 x i32> %val, i32 %element) {
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; CHECK-LABEL: f8:
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; CHECK: vlvgf %v24, %r2, 3
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; CHECK: br %r14
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%ret = insertelement <4 x i32> %val, i32 %element, i32 3
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ret <4 x i32> %ret
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}
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; Test v4i32 insertion into a variable element.
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define <4 x i32> @f9(<4 x i32> %val, i32 %element, i32 %index) {
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; CHECK-LABEL: f9:
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; CHECK: vlvgf %v24, %r2, 0(%r3)
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; CHECK: br %r14
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%ret = insertelement <4 x i32> %val, i32 %element, i32 %index
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ret <4 x i32> %ret
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}
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; Test v2i64 insertion into the first element.
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define <2 x i64> @f10(<2 x i64> %val, i64 %element) {
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; CHECK-LABEL: f10:
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; CHECK: vlvgg %v24, %r2, 0
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; CHECK: br %r14
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%ret = insertelement <2 x i64> %val, i64 %element, i32 0
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ret <2 x i64> %ret
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}
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; Test v2i64 insertion into the last element.
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define <2 x i64> @f11(<2 x i64> %val, i64 %element) {
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; CHECK-LABEL: f11:
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; CHECK: vlvgg %v24, %r2, 1
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; CHECK: br %r14
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%ret = insertelement <2 x i64> %val, i64 %element, i32 1
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ret <2 x i64> %ret
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}
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; Test v2i64 insertion into a variable element.
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define <2 x i64> @f12(<2 x i64> %val, i64 %element, i32 %index) {
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; CHECK-LABEL: f12:
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; CHECK: vlvgg %v24, %r2, 0(%r3)
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; CHECK: br %r14
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%ret = insertelement <2 x i64> %val, i64 %element, i32 %index
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ret <2 x i64> %ret
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}
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; Test v8f16 insertion into the first element.
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define <8 x half> @f13(<8 x half> %val, half %element) {
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; CHECK-LABEL: f13:
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; CHECK: lgdr %r0, %f0
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; CHECK: srlg %r0, %r0, 48
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; CHECK: vlvgh %v24, %r0, 0
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; CHECK: br %r14
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%ret = insertelement <8 x half> %val, half %element, i32 0
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ret <8 x half> %ret
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}
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; Test v8f16 insertion into the last element.
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define <8 x half> @f14(<8 x half> %val, half %element) {
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; CHECK-LABEL: f14:
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; CHECK: lgdr %r0, %f0
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; CHECK: srlg %r0, %r0, 48
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; CHECK: vlvgh %v24, %r0, 7
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; CHECK: br %r14
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%ret = insertelement <8 x half> %val, half %element, i32 7
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ret <8 x half> %ret
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}
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; Test v8f16 insertion into a variable element.
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define <8 x half> @f15(<8 x half> %val, half %element, i32 %index) {
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; CHECK-LABEL: f15:
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; CHECK: lgdr %r0, %f0
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; CHECK: srlg %r0, %r0, 48
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; CHECK: vlvgh %v24, %r0, 0(%r2)
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; CHECK: br %r14
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%ret = insertelement <8 x half> %val, half %element, i32 %index
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ret <8 x half> %ret
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}
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; Test v4f32 insertion into the first element.
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define <4 x float> @f16(<4 x float> %val, float %element) {
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; CHECK-LABEL: f16:
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; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
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; CHECK: vlvgf %v24, [[REG]], 0
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; CHECK: br %r14
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%ret = insertelement <4 x float> %val, float %element, i32 0
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ret <4 x float> %ret
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}
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; Test v4f32 insertion into the last element.
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define <4 x float> @f17(<4 x float> %val, float %element) {
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; CHECK-LABEL: f17:
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; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
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; CHECK: vlvgf %v24, [[REG]], 3
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; CHECK: br %r14
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%ret = insertelement <4 x float> %val, float %element, i32 3
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ret <4 x float> %ret
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}
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; Test v4f32 insertion into a variable element.
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define <4 x float> @f18(<4 x float> %val, float %element, i32 %index) {
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; CHECK-LABEL: f18:
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; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
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; CHECK: vlvgf %v24, [[REG]], 0(%r2)
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; CHECK: br %r14
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%ret = insertelement <4 x float> %val, float %element, i32 %index
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ret <4 x float> %ret
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}
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; Test v2f64 insertion into the first element.
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define <2 x double> @f19(<2 x double> %val, double %element) {
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; CHECK-LABEL: f19:
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; CHECK: vpdi %v24, %v0, %v24, 1
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; CHECK: br %r14
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%ret = insertelement <2 x double> %val, double %element, i32 0
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ret <2 x double> %ret
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}
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; Test v2f64 insertion into the last element.
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define <2 x double> @f20(<2 x double> %val, double %element) {
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; CHECK-LABEL: f20:
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; CHECK: vpdi %v24, %v24, %v0, 0
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; CHECK: br %r14
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%ret = insertelement <2 x double> %val, double %element, i32 1
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ret <2 x double> %ret
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}
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; Test v2f64 insertion into a variable element.
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define <2 x double> @f21(<2 x double> %val, double %element, i32 %index) {
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; CHECK-LABEL: f21:
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; CHECK: lgdr [[REG:%r[0-5]]], %f0
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; CHECK: vlvgg %v24, [[REG]], 0(%r2)
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; CHECK: br %r14
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%ret = insertelement <2 x double> %val, double %element, i32 %index
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ret <2 x double> %ret
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}
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; Test v16i8 insertion into a variable element plus one.
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define <16 x i8> @f22(<16 x i8> %val, i8 %element, i32 %index) {
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; CHECK-LABEL: f22:
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; CHECK: vlvgb %v24, %r2, 1(%r3)
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; CHECK: br %r14
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%add = add i32 %index, 1
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%ret = insertelement <16 x i8> %val, i8 %element, i32 %add
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ret <16 x i8> %ret
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}
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