4d629f9744
In review of bbde6b, I had originally proposed that we support the legacy text format. As review evolved, it bacame clear this had been a bad idea (too much complexity), but in order to let that patch finally move forward, I approved the change with the variant. This change undoes the variant, and updates all the tests to just use the array form.
162 lines
6.6 KiB
YAML
162 lines
6.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main"
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define void @ne_trip_count(i1 zeroext %t1, ptr nocapture %a, ptr nocapture readonly %b, i32 %N) #0 {
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entry:
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%0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
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br i1 %0, label %do.body.preheader, label %if.end
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do.body.preheader: ; preds = %entry
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%scevgep2 = getelementptr i32, ptr %a, i32 -1
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%scevgep5 = getelementptr i32, ptr %b, i32 -1
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br label %do.body
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do.body: ; preds = %do.body, %do.body.preheader
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%lsr.iv6 = phi ptr [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ]
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%lsr.iv = phi ptr [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ]
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%1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ]
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%scevgep = getelementptr i32, ptr %lsr.iv6, i32 1
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%scevgep1 = getelementptr i32, ptr %lsr.iv, i32 1
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%size = call i32 @llvm.arm.space(i32 4096, i32 undef)
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%tmp = load i32, ptr %scevgep, align 4
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store i32 %tmp, ptr %scevgep1, align 4
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%2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
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%3 = icmp ne i32 %2, 0
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%scevgep3 = getelementptr i32, ptr %lsr.iv, i32 1
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%scevgep7 = getelementptr i32, ptr %lsr.iv6, i32 1
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br i1 %3, label %do.body, label %if.end
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if.end: ; preds = %do.body, %entry
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ret void
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}
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declare i32 @llvm.arm.space(i32 immarg, i32) #1
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declare i1 @llvm.test.set.loop.iterations.i32(i32) #2
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2
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attributes #0 = { "target-features"="+lob" }
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attributes #1 = { nounwind }
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attributes #2 = { noduplicate nounwind }
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...
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---
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name: ne_trip_count
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: ne_trip_count
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: liveins: $lr, $r1, $r2, $r3, $r7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK-NEXT: dead $lr = t2SUBri $r3, 0, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK-NEXT: t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr
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; CHECK-NEXT: tB %bb.1, 14 /* CC::al */, $noreg
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.do.body.preheader:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $r1, $r2, $r3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.do.body:
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; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK-NEXT: liveins: $lr, $r0, $r1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead renamable $r2 = SPACE 4096, undef renamable $r0
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; CHECK-NEXT: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep)
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; CHECK-NEXT: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1)
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; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK-NEXT: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
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; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.if.end:
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; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.3(0x40000000)
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liveins: $r1, $r2, $r3, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$lr = t2WhileLoopStartLR $r3, %bb.3, implicit-def dead $cpsr
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tB %bb.1, 14, $noreg
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bb.1.do.body.preheader:
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successors: %bb.2(0x80000000)
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liveins: $r1, $r2, $r3
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renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
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$lr = tMOVr killed $r3, 14, $noreg
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bb.2.do.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $r0, $r1
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dead renamable $r2 = SPACE 4096, undef renamable $r0
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renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load (s32) from %ir.scevgep)
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early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store (s32) into %ir.scevgep1)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.if.end:
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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