4d629f9744
In review of bbde6b, I had originally proposed that we support the legacy text format. As review evolved, it bacame clear this had been a bad idea (too much complexity), but in order to let that patch finally move forward, I approved the change with the variant. This change undoes the variant, and updates all the tests to just use the array form.
153 lines
6.1 KiB
YAML
153 lines
6.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
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# TODO: Remove the lr = tMOVr which actually makes the WLS def dead!
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main"
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define dso_local arm_aapcscc void @copy(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) {
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entry:
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%0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
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br i1 %0, label %while.body.preheader, label %while.end
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while.body.preheader: ; preds = %entry
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%scevgep = getelementptr i16, ptr %a, i32 -1
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%scevgep3 = getelementptr i16, ptr %b, i32 -1
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br label %while.body
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while.body: ; preds = %while.body, %while.body.preheader
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%lsr.iv4 = phi ptr [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
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%lsr.iv = phi ptr [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
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%1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]
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%scevgep7 = getelementptr i16, ptr %lsr.iv, i32 1
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%scevgep4 = getelementptr i16, ptr %lsr.iv4, i32 1
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%2 = load i16, ptr %scevgep4, align 2
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store i16 %2, ptr %scevgep7, align 2
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%3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
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%4 = icmp ne i32 %3, 0
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%scevgep1 = getelementptr i16, ptr %lsr.iv, i32 1
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%scevgep5 = getelementptr i16, ptr %lsr.iv4, i32 1
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br i1 %4, label %while.body, label %while.end
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
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attributes #0 = { noduplicate nounwind }
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attributes #1 = { nounwind }
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...
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---
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name: copy
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: []
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restorePoint: []
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: copy
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK-NEXT: dead $lr = t2WLS $r2, %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.while.body.preheader:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $r0, $r1, $r2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg
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; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg
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; CHECK-NEXT: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.while.body:
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; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK-NEXT: liveins: $lr, $r0, $r1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.scevgep4)
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; CHECK-NEXT: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.scevgep7)
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; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.while.end:
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; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.3(0x40000000)
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liveins: $r0, $r1, $r2, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$lr = t2WhileLoopStartLR $r2, %bb.3, implicit-def dead $cpsr
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tB %bb.1, 14, $noreg
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
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renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
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$lr = tMOVr killed $r2, 14, $noreg
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bb.2.while.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $r0, $r1
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renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load (s16) from %ir.scevgep4)
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early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store (s16) into %ir.scevgep7)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.while.end:
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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