418 lines
20 KiB
LLVM
418 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
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; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S %s | FileCheck --check-prefix=VF4 %s
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; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -S %s | FileCheck --check-prefix=IC2 %s
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; rdar://problem/12848162
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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@a = common global [2048 x i32] zeroinitializer, align 16
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define void @example12() {
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; VF4-LABEL: define void @example12() {
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; VF4-NEXT: [[ENTRY:.*:]]
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; VF4-NEXT: br label %[[VECTOR_PH:.*]]
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; VF4: [[VECTOR_PH]]:
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; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
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; VF4: [[VECTOR_BODY]]:
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; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
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; VF4-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP0]], align 4
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; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
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; VF4-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
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; VF4-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; VF4: [[MIDDLE_BLOCK]]:
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; VF4-NEXT: br label %[[EXIT:.*]]
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; VF4: [[EXIT]]:
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; VF4-NEXT: ret void
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;
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; IC2-LABEL: define void @example12() {
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; IC2-NEXT: [[ENTRY:.*:]]
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; IC2-NEXT: br label %[[VECTOR_PH:.*]]
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; IC2: [[VECTOR_PH]]:
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; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
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; IC2: [[VECTOR_BODY]]:
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; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1
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; IC2-NEXT: [[TMP1:%.*]] = trunc i64 [[INDEX]] to i32
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; IC2-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
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; IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
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; IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP0]]
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; IC2-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4
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; IC2-NEXT: store i32 [[TMP2]], ptr [[TMP4]], align 4
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; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; IC2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
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; IC2-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; IC2: [[MIDDLE_BLOCK]]:
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; IC2-NEXT: br label %[[EXIT:.*]]
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; IC2: [[EXIT]]:
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; IC2-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %iv
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%iv.trunc = trunc i64 %iv to i32
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store i32 %iv.trunc, ptr %gep, align 4
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%iv.next = add i64 %iv, 1
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%iv.next.trunc = trunc i64 %iv.next to i32
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%exitcond = icmp eq i32 %iv.next.trunc, 1024
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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define void @redundant_iv_cast(ptr %dst) {
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; VF4-LABEL: define void @redundant_iv_cast(
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; VF4-SAME: ptr [[DST:%.*]]) {
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; VF4-NEXT: [[ENTRY:.*:]]
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; VF4-NEXT: br label %[[VECTOR_PH:.*]]
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; VF4: [[VECTOR_PH]]:
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; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
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; VF4: [[VECTOR_BODY]]:
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; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ <i16 0, i16 1, i16 2, i16 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16
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; VF4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[OFFSET_IDX]]
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; VF4-NEXT: store <4 x i16> [[VEC_IND]], ptr [[TMP0]], align 2
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; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[VEC_IND]], splat (i16 4)
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; VF4-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10000
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; VF4-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; VF4: [[MIDDLE_BLOCK]]:
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; VF4-NEXT: br label %[[SCALAR_PH:.*]]
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; VF4: [[SCALAR_PH]]:
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; VF4-NEXT: br label %[[LOOP:.*]]
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; VF4: [[LOOP]]:
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; VF4-NEXT: [[J_0:%.*]] = phi i16 [ 10000, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[LOOP]] ]
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; VF4-NEXT: [[EXT:%.*]] = zext i16 [[J_0]] to i32
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; VF4-NEXT: [[TRUNC:%.*]] = trunc i32 [[EXT]] to i16
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; VF4-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[J_0]]
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; VF4-NEXT: store i16 [[TRUNC]], ptr [[GEP]], align 2
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; VF4-NEXT: [[TMP2:%.*]] = icmp eq i16 10000, [[J_0]]
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; VF4-NEXT: [[INC]] = add i16 [[J_0]], 1
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; VF4-NEXT: br i1 [[TMP2]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
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; VF4: [[EXIT]]:
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; VF4-NEXT: ret void
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;
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; IC2-LABEL: define void @redundant_iv_cast(
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; IC2-SAME: ptr [[DST:%.*]]) {
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; IC2-NEXT: [[ENTRY:.*:]]
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; IC2-NEXT: br label %[[VECTOR_PH:.*]]
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; IC2: [[VECTOR_PH]]:
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; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
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; IC2: [[VECTOR_BODY]]:
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; IC2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IC2-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16
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; IC2-NEXT: [[TMP0:%.*]] = add i16 [[OFFSET_IDX]], 1
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; IC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[OFFSET_IDX]]
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; IC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[TMP0]]
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; IC2-NEXT: store i16 [[OFFSET_IDX]], ptr [[TMP1]], align 2
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; IC2-NEXT: store i16 [[TMP0]], ptr [[TMP2]], align 2
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; IC2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; IC2-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10000
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; IC2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; IC2: [[MIDDLE_BLOCK]]:
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; IC2-NEXT: br label %[[SCALAR_PH:.*]]
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; IC2: [[SCALAR_PH]]:
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; IC2-NEXT: br label %[[LOOP:.*]]
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; IC2: [[LOOP]]:
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; IC2-NEXT: [[J_0:%.*]] = phi i16 [ 10000, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[LOOP]] ]
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; IC2-NEXT: [[EXT:%.*]] = zext i16 [[J_0]] to i32
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; IC2-NEXT: [[TRUNC:%.*]] = trunc i32 [[EXT]] to i16
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; IC2-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[J_0]]
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; IC2-NEXT: store i16 [[TRUNC]], ptr [[GEP]], align 2
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; IC2-NEXT: [[TMP4:%.*]] = icmp eq i16 10000, [[J_0]]
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; IC2-NEXT: [[INC]] = add i16 [[J_0]], 1
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; IC2-NEXT: br i1 [[TMP4]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
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; IC2: [[EXIT]]:
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; IC2-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%j.0 = phi i16 [ 0, %entry ], [ %inc, %loop ]
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%ext = zext i16 %j.0 to i32
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%trunc = trunc i32 %ext to i16
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%gep = getelementptr inbounds i16, ptr %dst, i16 %j.0
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store i16 %trunc, ptr %gep
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%0 = icmp eq i16 10000, %j.0
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%inc = add i16 %j.0, 1
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br i1 %0, label %exit, label %loop
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exit:
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ret void
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}
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define void @cast_variable_step(i64 %step) {
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; VF4-LABEL: define void @cast_variable_step(
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; VF4-SAME: i64 [[STEP:%.*]]) {
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; VF4-NEXT: [[ENTRY:.*:]]
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; VF4-NEXT: br label %[[VECTOR_PH:.*]]
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; VF4: [[VECTOR_PH]]:
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; VF4-NEXT: [[TMP0:%.*]] = trunc i64 [[STEP]] to i32
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; VF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
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; VF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
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; VF4-NEXT: [[TMP1:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[BROADCAST_SPLAT]]
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; VF4-NEXT: [[INDUCTION:%.*]] = add <4 x i32> splat (i32 10), [[TMP1]]
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; VF4-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], 2
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; VF4-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 0
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; VF4-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer
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; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
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; VF4: [[VECTOR_BODY]]:
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; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
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; VF4-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP3]], align 4
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; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
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; VF4-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
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; VF4-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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; VF4: [[MIDDLE_BLOCK]]:
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; VF4-NEXT: br label %[[EXIT:.*]]
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; VF4: [[EXIT]]:
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; VF4-NEXT: ret void
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;
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; IC2-LABEL: define void @cast_variable_step(
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; IC2-SAME: i64 [[STEP:%.*]]) {
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; IC2-NEXT: [[ENTRY:.*:]]
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; IC2-NEXT: br label %[[VECTOR_PH:.*]]
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; IC2: [[VECTOR_PH]]:
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; IC2-NEXT: [[TMP0:%.*]] = trunc i64 [[STEP]] to i32
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; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
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; IC2: [[VECTOR_BODY]]:
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; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
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; IC2-NEXT: [[TMP2:%.*]] = mul i64 [[INDEX]], [[STEP]]
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; IC2-NEXT: [[OFFSET_IDX:%.*]] = add i64 10, [[TMP2]]
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; IC2-NEXT: [[TMP3:%.*]] = trunc i64 [[OFFSET_IDX]] to i32
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; IC2-NEXT: [[TMP4:%.*]] = mul i32 1, [[TMP0]]
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; IC2-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], [[TMP4]]
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; IC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
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; IC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP1]]
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; IC2-NEXT: store i32 [[TMP3]], ptr [[TMP6]], align 4
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; IC2-NEXT: store i32 [[TMP5]], ptr [[TMP7]], align 4
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; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; IC2-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
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; IC2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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; IC2: [[MIDDLE_BLOCK]]:
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; IC2-NEXT: br label %[[EXIT:.*]]
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; IC2: [[EXIT]]:
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; IC2-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv.1 = phi i64 [ 10, %entry ], [ %iv.1.next, %loop ]
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%gep = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %iv
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%iv.1.trunc = trunc i64 %iv.1 to i32
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store i32 %iv.1.trunc, ptr %gep, align 4
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%iv.next = add i64 %iv, 1
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%iv.1.next = add i64 %iv.1, %step
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%exitcond = icmp eq i64 %iv.next, 1024
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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define void @cast_induction_tail_folding(ptr %A) {
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; VF4-LABEL: define void @cast_induction_tail_folding(
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; VF4-SAME: ptr [[A:%.*]]) {
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; VF4-NEXT: [[ENTRY:.*:]]
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; VF4-NEXT: br label %[[VECTOR_PH:.*]]
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; VF4: [[VECTOR_PH]]:
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; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
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; VF4: [[VECTOR_BODY]]:
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; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
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; VF4: [[PRED_STORE_IF]]:
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; VF4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 0
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; VF4-NEXT: store i32 0, ptr [[TMP0]], align 4
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; VF4-NEXT: br label %[[PRED_STORE_CONTINUE]]
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; VF4: [[PRED_STORE_CONTINUE]]:
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; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
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; VF4: [[PRED_STORE_IF1]]:
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; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 1
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; VF4-NEXT: store i32 1, ptr [[TMP1]], align 4
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; VF4-NEXT: br label %[[PRED_STORE_CONTINUE2]]
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; VF4: [[PRED_STORE_CONTINUE2]]:
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; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
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; VF4: [[PRED_STORE_IF3]]:
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; VF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 2
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; VF4-NEXT: store i32 2, ptr [[TMP2]], align 4
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; VF4-NEXT: br label %[[PRED_STORE_CONTINUE4]]
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; VF4: [[PRED_STORE_CONTINUE4]]:
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; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
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; VF4: [[PRED_STORE_IF5]]:
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; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 3
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; VF4-NEXT: store i32 3, ptr [[TMP3]], align 4
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; VF4-NEXT: br label %[[PRED_STORE_CONTINUE6]]
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; VF4: [[PRED_STORE_CONTINUE6]]:
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; VF4-NEXT: br label %[[MIDDLE_BLOCK:.*]]
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; VF4: [[MIDDLE_BLOCK]]:
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; VF4-NEXT: br label %[[EXIT:.*]]
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; VF4: [[EXIT]]:
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; VF4-NEXT: ret void
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;
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; IC2-LABEL: define void @cast_induction_tail_folding(
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; IC2-SAME: ptr [[A:%.*]]) {
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; IC2-NEXT: [[ENTRY:.*:]]
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; IC2-NEXT: br label %[[VECTOR_PH:.*]]
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; IC2: [[VECTOR_PH]]:
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; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
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; IC2: [[VECTOR_BODY]]:
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; IC2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE2:.*]] ]
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; IC2-NEXT: [[INDEX0:%.*]] = add i32 [[INDEX]], 0
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; IC2-NEXT: [[INDEX1:%.*]] = add i32 [[INDEX]], 1
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; IC2-NEXT: [[TMP2:%.*]] = icmp ule i32 [[INDEX0]], 2
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; IC2-NEXT: [[TMP3:%.*]] = icmp ule i32 [[INDEX1]], 2
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; IC2-NEXT: br i1 [[TMP2]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
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; IC2: [[PRED_STORE_IF]]:
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; IC2-NEXT: [[TMP4:%.*]] = sext i32 [[INDEX0]] to i64
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; IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]]
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; IC2-NEXT: store i32 [[INDEX0]], ptr [[TMP5]], align 4
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; IC2-NEXT: br label %[[PRED_STORE_CONTINUE]]
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; IC2: [[PRED_STORE_CONTINUE]]:
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; IC2-NEXT: br i1 [[TMP3]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2]]
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; IC2: [[PRED_STORE_IF1]]:
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; IC2-NEXT: [[TMP6:%.*]] = sext i32 [[INDEX1]] to i64
|
|
; IC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]]
|
|
; IC2-NEXT: store i32 [[INDEX1]], ptr [[TMP7]], align 4
|
|
; IC2-NEXT: br label %[[PRED_STORE_CONTINUE2]]
|
|
; IC2: [[PRED_STORE_CONTINUE2]]:
|
|
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
|
|
; IC2-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
|
|
; IC2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
; IC2: [[MIDDLE_BLOCK]]:
|
|
; IC2-NEXT: br label %[[EXIT:.*]]
|
|
; IC2: [[EXIT]]:
|
|
; IC2-NEXT: ret void
|
|
;
|
|
|
|
entry:
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
|
|
%iv.ext = sext i32 %iv to i64
|
|
%iv.trunc = trunc i64 %iv.ext to i32
|
|
%gep = getelementptr inbounds i32, ptr %A, i64 %iv.ext
|
|
store i32 %iv.trunc, ptr %gep
|
|
%iv.next = add i32 %iv, 1
|
|
%c = icmp slt i32 %iv.next, 3
|
|
br i1 %c, label %loop, label %exit
|
|
|
|
exit:
|
|
ret void
|
|
}
|
|
|
|
define void @test_start_zext(i32 %start, ptr %dst) {
|
|
; VF4-LABEL: define void @test_start_zext(
|
|
; VF4-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) {
|
|
; VF4-NEXT: [[ENTRY:.*:]]
|
|
; VF4-NEXT: [[START_EXT:%.*]] = zext i32 [[START]] to i64
|
|
; VF4-NEXT: [[TMP0:%.*]] = sub i64 100, [[START_EXT]]
|
|
; VF4-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
|
|
; VF4: [[VECTOR_SCEVCHECK]]:
|
|
; VF4-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[START]], 1
|
|
; VF4-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
|
|
; VF4: [[VECTOR_PH]]:
|
|
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
|
|
; VF4: [[VECTOR_BODY]]:
|
|
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
|
; VF4-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[DST]], i64 [[INDEX]]
|
|
; VF4-NEXT: store <4 x float> zeroinitializer, ptr [[TMP1]], align 4
|
|
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
|
|
; VF4-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
|
|
; VF4-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
|
|
; VF4: [[MIDDLE_BLOCK]]:
|
|
; VF4-NEXT: br label %[[SCALAR_PH]]
|
|
; VF4: [[SCALAR_PH]]:
|
|
; VF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 97, %[[MIDDLE_BLOCK]] ], [ [[START_EXT]], %[[VECTOR_SCEVCHECK]] ]
|
|
; VF4-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ 96, %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
|
|
; VF4-NEXT: br label %[[LOOP:.*]]
|
|
; VF4: [[LOOP]]:
|
|
; VF4-NEXT: [[IV_0:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP]] ]
|
|
; VF4-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]
|
|
; VF4-NEXT: [[GEP_DST:%.*]] = getelementptr float, ptr [[DST]], i64 [[IV_1]]
|
|
; VF4-NEXT: store float 0.000000e+00, ptr [[GEP_DST]], align 4
|
|
; VF4-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], [[START_EXT]]
|
|
; VF4-NEXT: [[IV_0_NEXT]] = add i64 [[IV_0]], 1
|
|
; VF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_0_NEXT]], 100
|
|
; VF4-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
; VF4: [[EXIT]]:
|
|
; VF4-NEXT: ret void
|
|
;
|
|
; IC2-LABEL: define void @test_start_zext(
|
|
; IC2-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) {
|
|
; IC2-NEXT: [[ENTRY:.*]]:
|
|
; IC2-NEXT: [[START_EXT:%.*]] = zext i32 [[START]] to i64
|
|
; IC2-NEXT: [[TMP0:%.*]] = sub i64 100, [[START_EXT]]
|
|
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
|
|
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
|
|
; IC2: [[VECTOR_PH]]:
|
|
; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
|
|
; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
|
|
; IC2-NEXT: [[TMP1:%.*]] = add i64 [[START_EXT]], [[N_VEC]]
|
|
; IC2-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], [[START_EXT]]
|
|
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
|
|
; IC2: [[VECTOR_BODY]]:
|
|
; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
|
; IC2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[START_EXT]]
|
|
; IC2-NEXT: [[TMP3:%.*]] = mul i64 1, [[START_EXT]]
|
|
; IC2-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], [[TMP3]]
|
|
; IC2-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[DST]], i64 [[OFFSET_IDX]]
|
|
; IC2-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[DST]], i64 [[TMP4]]
|
|
; IC2-NEXT: store float 0.000000e+00, ptr [[TMP5]], align 4
|
|
; IC2-NEXT: store float 0.000000e+00, ptr [[TMP6]], align 4
|
|
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
|
; IC2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
|
; IC2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
|
|
; IC2: [[MIDDLE_BLOCK]]:
|
|
; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
|
|
; IC2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
|
; IC2: [[SCALAR_PH]]:
|
|
; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[START_EXT]], %[[ENTRY]] ]
|
|
; IC2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
|
|
; IC2-NEXT: br label %[[LOOP:.*]]
|
|
; IC2: [[LOOP]]:
|
|
; IC2-NEXT: [[IV_0:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP]] ]
|
|
; IC2-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]
|
|
; IC2-NEXT: [[GEP_DST:%.*]] = getelementptr float, ptr [[DST]], i64 [[IV_1]]
|
|
; IC2-NEXT: store float 0.000000e+00, ptr [[GEP_DST]], align 4
|
|
; IC2-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], [[START_EXT]]
|
|
; IC2-NEXT: [[IV_0_NEXT]] = add i64 [[IV_0]], 1
|
|
; IC2-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_0_NEXT]], 100
|
|
; IC2-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
|
|
; IC2: [[EXIT]]:
|
|
; IC2-NEXT: ret void
|
|
;
|
|
entry:
|
|
%start.ext = zext i32 %start to i64
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv.0 = phi i64 [ %start.ext, %entry ], [ %iv.0.next, %loop ]
|
|
%iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
|
|
%gep.dst = getelementptr float, ptr %dst, i64 %iv.1
|
|
store float 0.0, ptr %gep.dst, align 4
|
|
%iv.1.next = add i64 %iv.1, %start.ext
|
|
%iv.0.next = add i64 %iv.0, 1
|
|
%ec = icmp eq i64 %iv.0.next, 100
|
|
br i1 %ec, label %exit, label %loop
|
|
|
|
exit:
|
|
ret void
|
|
}
|