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llvm-project/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
Alexey Bataev 1a8f5fa823 [SLP]Exclude non-profitable subtrees. 
Initial support for SLP tree throttling. Trims non-profitable subtrees,
trying to maximize perf gains.

Does not support trees with gathered loads yet, since they are not quite
trees, but graphs. Analysis should be added later.

Reviewers: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/162018

Recommit after revert in 6ec2ec4826b51d7d809fe08b36883a78d7dc0b98 with
a fix
2025-12-30 09:32:05 -08:00

1101 lines
75 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v | FileCheck %s
; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-15 | FileCheck %s --check-prefix=THR15
; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v,+unaligned-vector-mem | FileCheck %s --check-prefix=UNALIGNED_VEC_MEM
define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.ptr, ptr %add.ptr64) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4
; CHECK-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
; CHECK-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
; CHECK-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4
; CHECK-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4
; CHECK-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
; CHECK-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
; CHECK-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
; CHECK-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
; CHECK-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4
; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 1
; CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr null, align 1
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PIX1]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[PIX2]], align 1
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[TMP3]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>
; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 1
; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i32>
; CHECK-NEXT: [[TMP11:%.*]] = sub <4 x i32> [[TMP8]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = shl <4 x i32> [[TMP11]], splat (i32 16)
; CHECK-NEXT: [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP6]]
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; CHECK-NEXT: [[TMP15:%.*]] = add <4 x i32> [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP14]], [[TMP13]]
; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP15]], <4 x i32> [[TMP16]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP19:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]
; CHECK-NEXT: [[TMP20:%.*]] = sub <4 x i32> [[TMP17]], [[TMP18]]
; CHECK-NEXT: [[TMP88:%.*]] = shufflevector <4 x i32> [[TMP19]], <4 x i32> [[TMP20]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP22:%.*]] = load <4 x i8>, ptr [[ADD_PTR3]], align 1
; CHECK-NEXT: [[TMP23:%.*]] = zext <4 x i8> [[TMP22]] to <4 x i32>
; CHECK-NEXT: [[TMP24:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = zext <4 x i8> [[TMP24]] to <4 x i32>
; CHECK-NEXT: [[TMP26:%.*]] = sub <4 x i32> [[TMP23]], [[TMP25]]
; CHECK-NEXT: [[TMP27:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 1
; CHECK-NEXT: [[TMP28:%.*]] = zext <4 x i8> [[TMP27]] to <4 x i32>
; CHECK-NEXT: [[TMP29:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 1
; CHECK-NEXT: [[TMP30:%.*]] = zext <4 x i8> [[TMP29]] to <4 x i32>
; CHECK-NEXT: [[TMP31:%.*]] = sub <4 x i32> [[TMP28]], [[TMP30]]
; CHECK-NEXT: [[TMP32:%.*]] = shl <4 x i32> [[TMP31]], splat (i32 16)
; CHECK-NEXT: [[TMP33:%.*]] = add <4 x i32> [[TMP32]], [[TMP26]]
; CHECK-NEXT: [[TMP34:%.*]] = shufflevector <4 x i32> [[TMP33]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; CHECK-NEXT: [[TMP35:%.*]] = add <4 x i32> [[TMP34]], [[TMP33]]
; CHECK-NEXT: [[TMP36:%.*]] = sub <4 x i32> [[TMP34]], [[TMP33]]
; CHECK-NEXT: [[TMP37:%.*]] = shufflevector <4 x i32> [[TMP35]], <4 x i32> [[TMP36]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP38:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP39:%.*]] = add <4 x i32> [[TMP37]], [[TMP38]]
; CHECK-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP37]], [[TMP38]]
; CHECK-NEXT: [[TMP89:%.*]] = shufflevector <4 x i32> [[TMP39]], <4 x i32> [[TMP40]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT: [[TMP42:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 1
; CHECK-NEXT: [[TMP43:%.*]] = zext <4 x i8> [[TMP42]] to <4 x i32>
; CHECK-NEXT: [[TMP44:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 1
; CHECK-NEXT: [[TMP45:%.*]] = zext <4 x i8> [[TMP44]] to <4 x i32>
; CHECK-NEXT: [[TMP46:%.*]] = sub <4 x i32> [[TMP43]], [[TMP45]]
; CHECK-NEXT: [[TMP47:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 1
; CHECK-NEXT: [[TMP48:%.*]] = zext <4 x i8> [[TMP47]] to <4 x i32>
; CHECK-NEXT: [[TMP49:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 1
; CHECK-NEXT: [[TMP50:%.*]] = zext <4 x i8> [[TMP49]] to <4 x i32>
; CHECK-NEXT: [[TMP51:%.*]] = sub <4 x i32> [[TMP48]], [[TMP50]]
; CHECK-NEXT: [[TMP52:%.*]] = shl <4 x i32> [[TMP51]], splat (i32 16)
; CHECK-NEXT: [[TMP53:%.*]] = add <4 x i32> [[TMP52]], [[TMP46]]
; CHECK-NEXT: [[TMP54:%.*]] = shufflevector <4 x i32> [[TMP53]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; CHECK-NEXT: [[TMP55:%.*]] = add <4 x i32> [[TMP54]], [[TMP53]]
; CHECK-NEXT: [[TMP56:%.*]] = sub <4 x i32> [[TMP54]], [[TMP53]]
; CHECK-NEXT: [[TMP57:%.*]] = shufflevector <4 x i32> [[TMP55]], <4 x i32> [[TMP56]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP59:%.*]] = add <4 x i32> [[TMP57]], [[TMP58]]
; CHECK-NEXT: [[TMP60:%.*]] = sub <4 x i32> [[TMP57]], [[TMP58]]
; CHECK-NEXT: [[TMP61:%.*]] = shufflevector <4 x i32> [[TMP59]], <4 x i32> [[TMP60]], <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; CHECK-NEXT: [[TMP63:%.*]] = load <4 x i8>, ptr null, align 1
; CHECK-NEXT: [[TMP64:%.*]] = zext <4 x i8> [[TMP63]] to <4 x i32>
; CHECK-NEXT: [[TMP65:%.*]] = load <4 x i8>, ptr null, align 1
; CHECK-NEXT: [[TMP66:%.*]] = zext <4 x i8> [[TMP65]] to <4 x i32>
; CHECK-NEXT: [[TMP67:%.*]] = sub <4 x i32> [[TMP64]], [[TMP66]]
; CHECK-NEXT: [[TMP68:%.*]] = shufflevector <4 x i32> [[TMP67]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP71:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)
; CHECK-NEXT: [[TMP69:%.*]] = insertelement <2 x i8> poison, i8 [[TMP115]], i32 0
; CHECK-NEXT: [[TMP70:%.*]] = insertelement <2 x i8> [[TMP69]], i8 [[TMP0]], i32 1
; CHECK-NEXT: [[TMP73:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_3]], align 1
; CHECK-NEXT: [[TMP74:%.*]] = zext <4 x i8> [[TMP73]] to <4 x i32>
; CHECK-NEXT: [[TMP75:%.*]] = shufflevector <4 x i32> [[TMP74]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP117:%.*]] = zext <2 x i8> [[TMP70]] to <2 x i32>
; CHECK-NEXT: [[TMP119:%.*]] = shufflevector <2 x i32> [[TMP117]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP120:%.*]] = zext <2 x i8> [[TMP71]] to <2 x i32>
; CHECK-NEXT: [[TMP121:%.*]] = shufflevector <2 x i32> [[TMP120]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP72:%.*]] = shufflevector <4 x i32> [[TMP119]], <4 x i32> [[TMP121]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: [[TMP76:%.*]] = sub <4 x i32> [[TMP72]], [[TMP75]]
; CHECK-NEXT: [[TMP77:%.*]] = shl <4 x i32> [[TMP76]], splat (i32 16)
; CHECK-NEXT: [[TMP78:%.*]] = add <4 x i32> [[TMP77]], [[TMP68]]
; CHECK-NEXT: [[TMP79:%.*]] = shufflevector <4 x i32> [[TMP78]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; CHECK-NEXT: [[TMP80:%.*]] = add <4 x i32> [[TMP78]], [[TMP79]]
; CHECK-NEXT: [[TMP81:%.*]] = sub <4 x i32> [[TMP78]], [[TMP79]]
; CHECK-NEXT: [[TMP82:%.*]] = shufflevector <4 x i32> [[TMP80]], <4 x i32> [[TMP81]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; CHECK-NEXT: [[TMP83:%.*]] = shufflevector <4 x i32> [[TMP82]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP84:%.*]] = add <4 x i32> [[TMP82]], [[TMP83]]
; CHECK-NEXT: [[TMP85:%.*]] = sub <4 x i32> [[TMP82]], [[TMP83]]
; CHECK-NEXT: [[TMP86:%.*]] = shufflevector <4 x i32> [[TMP84]], <4 x i32> [[TMP85]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: [[TMP41:%.*]] = shufflevector <4 x i32> [[TMP89]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP88]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP87:%.*]] = add <4 x i32> [[TMP41]], [[TMP21]]
; CHECK-NEXT: [[TMP106:%.*]] = sub <4 x i32> [[TMP88]], [[TMP89]]
; CHECK-NEXT: [[TMP90:%.*]] = shufflevector <4 x i32> [[TMP106]], <4 x i32> [[TMP87]], <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[TMP91:%.*]] = add <4 x i32> [[TMP86]], [[TMP61]]
; CHECK-NEXT: [[TMP92:%.*]] = sub <4 x i32> [[TMP61]], [[TMP86]]
; CHECK-NEXT: [[TMP93:%.*]] = shufflevector <4 x i32> [[TMP92]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP118:%.*]] = shufflevector <4 x i32> [[TMP91]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP94:%.*]] = shufflevector <8 x i32> [[TMP93]], <8 x i32> [[TMP118]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[TMP95:%.*]] = add <8 x i32> [[TMP94]], [[TMP90]]
; CHECK-NEXT: [[TMP96:%.*]] = sub <8 x i32> [[TMP90]], [[TMP94]]
; CHECK-NEXT: [[TMP97:%.*]] = shufflevector <8 x i32> [[TMP95]], <8 x i32> [[TMP96]], <16 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7, i32 12, i32 8, i32 13, i32 9, i32 14, i32 10, i32 15, i32 11>
; CHECK-NEXT: [[TMP98:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> [[TMP64]], <16 x i32> <i32 2, i32 4, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP99:%.*]] = shufflevector <4 x i32> [[TMP43]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP100:%.*]] = shufflevector <16 x i32> [[TMP98]], <16 x i32> [[TMP99]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP101:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP102:%.*]] = shufflevector <16 x i32> [[TMP100]], <16 x i32> [[TMP101]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP103:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP104:%.*]] = shufflevector <16 x i32> [[TMP102]], <16 x i32> [[TMP103]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 poison, i32 18, i32 19>
; CHECK-NEXT: [[TMP105:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP116:%.*]] = shufflevector <16 x i32> [[TMP104]], <16 x i32> [[TMP105]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 18, i32 poison, i32 19, i32 poison, i32 12, i32 poison, i32 14, i32 15>
; CHECK-NEXT: [[TMP107:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP108:%.*]] = shufflevector <16 x i32> [[TMP116]], <16 x i32> [[TMP107]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 18, i32 10, i32 19, i32 12, i32 16, i32 14, i32 15>
; CHECK-NEXT: [[TMP109:%.*]] = lshr <16 x i32> [[TMP108]], splat (i32 15)
; CHECK-NEXT: [[TMP110:%.*]] = and <16 x i32> [[TMP109]], splat (i32 65537)
; CHECK-NEXT: [[TMP111:%.*]] = mul <16 x i32> [[TMP110]], splat (i32 65535)
; CHECK-NEXT: [[TMP112:%.*]] = add <16 x i32> [[TMP111]], [[TMP97]]
; CHECK-NEXT: [[TMP113:%.*]] = xor <16 x i32> [[TMP112]], [[TMP108]]
; CHECK-NEXT: [[TMP114:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP113]])
; CHECK-NEXT: ret i32 [[TMP114]]
;
; THR15-LABEL: define i32 @test(
; THR15-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
; THR15-NEXT: entry:
; THR15-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4
; THR15-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4
; THR15-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
; THR15-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
; THR15-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4
; THR15-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4
; THR15-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
; THR15-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
; THR15-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
; THR15-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
; THR15-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4
; THR15-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 1
; THR15-NEXT: [[TMP1:%.*]] = load i8, ptr null, align 1
; THR15-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PIX1]], align 1
; THR15-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
; THR15-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[PIX2]], align 1
; THR15-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>
; THR15-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[TMP3]], [[TMP5]]
; THR15-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3]], align 1
; THR15-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>
; THR15-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 1
; THR15-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i32>
; THR15-NEXT: [[TMP11:%.*]] = sub <4 x i32> [[TMP8]], [[TMP10]]
; THR15-NEXT: [[TMP12:%.*]] = shl <4 x i32> [[TMP11]], splat (i32 16)
; THR15-NEXT: [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP6]]
; THR15-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; THR15-NEXT: [[TMP15:%.*]] = add <4 x i32> [[TMP14]], [[TMP13]]
; THR15-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP14]], [[TMP13]]
; THR15-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP15]], <4 x i32> [[TMP16]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; THR15-NEXT: [[TMP18:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; THR15-NEXT: [[TMP19:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]
; THR15-NEXT: [[TMP20:%.*]] = sub <4 x i32> [[TMP17]], [[TMP18]]
; THR15-NEXT: [[TMP88:%.*]] = shufflevector <4 x i32> [[TMP19]], <4 x i32> [[TMP20]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; THR15-NEXT: [[TMP22:%.*]] = load <4 x i8>, ptr [[ADD_PTR3]], align 1
; THR15-NEXT: [[TMP23:%.*]] = zext <4 x i8> [[TMP22]] to <4 x i32>
; THR15-NEXT: [[TMP24:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 1
; THR15-NEXT: [[TMP25:%.*]] = zext <4 x i8> [[TMP24]] to <4 x i32>
; THR15-NEXT: [[TMP26:%.*]] = sub <4 x i32> [[TMP23]], [[TMP25]]
; THR15-NEXT: [[TMP27:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 1
; THR15-NEXT: [[TMP28:%.*]] = zext <4 x i8> [[TMP27]] to <4 x i32>
; THR15-NEXT: [[TMP29:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 1
; THR15-NEXT: [[TMP30:%.*]] = zext <4 x i8> [[TMP29]] to <4 x i32>
; THR15-NEXT: [[TMP31:%.*]] = sub <4 x i32> [[TMP28]], [[TMP30]]
; THR15-NEXT: [[TMP32:%.*]] = shl <4 x i32> [[TMP31]], splat (i32 16)
; THR15-NEXT: [[TMP33:%.*]] = add <4 x i32> [[TMP32]], [[TMP26]]
; THR15-NEXT: [[TMP34:%.*]] = shufflevector <4 x i32> [[TMP33]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; THR15-NEXT: [[TMP35:%.*]] = add <4 x i32> [[TMP34]], [[TMP33]]
; THR15-NEXT: [[TMP36:%.*]] = sub <4 x i32> [[TMP34]], [[TMP33]]
; THR15-NEXT: [[TMP37:%.*]] = shufflevector <4 x i32> [[TMP35]], <4 x i32> [[TMP36]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; THR15-NEXT: [[TMP38:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; THR15-NEXT: [[TMP39:%.*]] = add <4 x i32> [[TMP37]], [[TMP38]]
; THR15-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP37]], [[TMP38]]
; THR15-NEXT: [[TMP89:%.*]] = shufflevector <4 x i32> [[TMP39]], <4 x i32> [[TMP40]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; THR15-NEXT: [[TMP42:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 1
; THR15-NEXT: [[TMP43:%.*]] = zext <4 x i8> [[TMP42]] to <4 x i32>
; THR15-NEXT: [[TMP44:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 1
; THR15-NEXT: [[TMP45:%.*]] = zext <4 x i8> [[TMP44]] to <4 x i32>
; THR15-NEXT: [[TMP46:%.*]] = sub <4 x i32> [[TMP43]], [[TMP45]]
; THR15-NEXT: [[TMP47:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 1
; THR15-NEXT: [[TMP48:%.*]] = zext <4 x i8> [[TMP47]] to <4 x i32>
; THR15-NEXT: [[TMP49:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 1
; THR15-NEXT: [[TMP50:%.*]] = zext <4 x i8> [[TMP49]] to <4 x i32>
; THR15-NEXT: [[TMP51:%.*]] = sub <4 x i32> [[TMP48]], [[TMP50]]
; THR15-NEXT: [[TMP52:%.*]] = shl <4 x i32> [[TMP51]], splat (i32 16)
; THR15-NEXT: [[TMP53:%.*]] = add <4 x i32> [[TMP52]], [[TMP46]]
; THR15-NEXT: [[TMP54:%.*]] = shufflevector <4 x i32> [[TMP53]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; THR15-NEXT: [[TMP55:%.*]] = add <4 x i32> [[TMP54]], [[TMP53]]
; THR15-NEXT: [[TMP56:%.*]] = sub <4 x i32> [[TMP54]], [[TMP53]]
; THR15-NEXT: [[TMP57:%.*]] = shufflevector <4 x i32> [[TMP55]], <4 x i32> [[TMP56]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; THR15-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; THR15-NEXT: [[TMP59:%.*]] = add <4 x i32> [[TMP57]], [[TMP58]]
; THR15-NEXT: [[TMP60:%.*]] = sub <4 x i32> [[TMP57]], [[TMP58]]
; THR15-NEXT: [[TMP61:%.*]] = shufflevector <4 x i32> [[TMP59]], <4 x i32> [[TMP60]], <4 x i32> <i32 2, i32 3, i32 4, i32 5>
; THR15-NEXT: [[TMP62:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)
; THR15-NEXT: [[TMP63:%.*]] = load <4 x i8>, ptr null, align 1
; THR15-NEXT: [[TMP64:%.*]] = zext <4 x i8> [[TMP63]] to <4 x i32>
; THR15-NEXT: [[TMP65:%.*]] = load <4 x i8>, ptr null, align 1
; THR15-NEXT: [[TMP66:%.*]] = zext <4 x i8> [[TMP65]] to <4 x i32>
; THR15-NEXT: [[TMP67:%.*]] = sub <4 x i32> [[TMP64]], [[TMP66]]
; THR15-NEXT: [[TMP68:%.*]] = shufflevector <4 x i32> [[TMP67]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; THR15-NEXT: [[TMP69:%.*]] = insertelement <4 x i8> poison, i8 [[TMP1]], i32 0
; THR15-NEXT: [[TMP70:%.*]] = insertelement <4 x i8> [[TMP69]], i8 [[TMP0]], i32 1
; THR15-NEXT: [[TMP116:%.*]] = shufflevector <2 x i8> [[TMP62]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; THR15-NEXT: [[TMP71:%.*]] = shufflevector <4 x i8> [[TMP70]], <4 x i8> [[TMP116]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; THR15-NEXT: [[TMP72:%.*]] = zext <4 x i8> [[TMP71]] to <4 x i32>
; THR15-NEXT: [[TMP73:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_3]], align 1
; THR15-NEXT: [[TMP74:%.*]] = zext <4 x i8> [[TMP73]] to <4 x i32>
; THR15-NEXT: [[TMP75:%.*]] = shufflevector <4 x i32> [[TMP74]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; THR15-NEXT: [[TMP76:%.*]] = sub <4 x i32> [[TMP72]], [[TMP75]]
; THR15-NEXT: [[TMP77:%.*]] = shl <4 x i32> [[TMP76]], splat (i32 16)
; THR15-NEXT: [[TMP78:%.*]] = add <4 x i32> [[TMP77]], [[TMP68]]
; THR15-NEXT: [[TMP79:%.*]] = shufflevector <4 x i32> [[TMP78]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; THR15-NEXT: [[TMP80:%.*]] = add <4 x i32> [[TMP78]], [[TMP79]]
; THR15-NEXT: [[TMP81:%.*]] = sub <4 x i32> [[TMP78]], [[TMP79]]
; THR15-NEXT: [[TMP82:%.*]] = shufflevector <4 x i32> [[TMP80]], <4 x i32> [[TMP81]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; THR15-NEXT: [[TMP83:%.*]] = shufflevector <4 x i32> [[TMP82]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; THR15-NEXT: [[TMP84:%.*]] = add <4 x i32> [[TMP82]], [[TMP83]]
; THR15-NEXT: [[TMP85:%.*]] = sub <4 x i32> [[TMP82]], [[TMP83]]
; THR15-NEXT: [[TMP86:%.*]] = shufflevector <4 x i32> [[TMP84]], <4 x i32> [[TMP85]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; THR15-NEXT: [[TMP41:%.*]] = shufflevector <4 x i32> [[TMP89]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; THR15-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP88]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; THR15-NEXT: [[TMP87:%.*]] = add <4 x i32> [[TMP41]], [[TMP21]]
; THR15-NEXT: [[TMP106:%.*]] = sub <4 x i32> [[TMP88]], [[TMP89]]
; THR15-NEXT: [[TMP90:%.*]] = shufflevector <4 x i32> [[TMP106]], <4 x i32> [[TMP87]], <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>
; THR15-NEXT: [[TMP91:%.*]] = add <4 x i32> [[TMP86]], [[TMP61]]
; THR15-NEXT: [[TMP92:%.*]] = sub <4 x i32> [[TMP61]], [[TMP86]]
; THR15-NEXT: [[TMP93:%.*]] = shufflevector <4 x i32> [[TMP92]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP117:%.*]] = shufflevector <4 x i32> [[TMP91]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP94:%.*]] = shufflevector <8 x i32> [[TMP93]], <8 x i32> [[TMP117]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
; THR15-NEXT: [[TMP95:%.*]] = add <8 x i32> [[TMP94]], [[TMP90]]
; THR15-NEXT: [[TMP96:%.*]] = sub <8 x i32> [[TMP90]], [[TMP94]]
; THR15-NEXT: [[TMP97:%.*]] = shufflevector <8 x i32> [[TMP95]], <8 x i32> [[TMP96]], <16 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7, i32 12, i32 8, i32 13, i32 9, i32 14, i32 10, i32 15, i32 11>
; THR15-NEXT: [[TMP98:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> [[TMP64]], <16 x i32> <i32 2, i32 4, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP99:%.*]] = shufflevector <4 x i32> [[TMP43]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP100:%.*]] = shufflevector <16 x i32> [[TMP98]], <16 x i32> [[TMP99]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP101:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP102:%.*]] = shufflevector <16 x i32> [[TMP100]], <16 x i32> [[TMP101]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP103:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP104:%.*]] = shufflevector <16 x i32> [[TMP102]], <16 x i32> [[TMP103]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 poison, i32 18, i32 19>
; THR15-NEXT: [[TMP105:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP115:%.*]] = shufflevector <16 x i32> [[TMP104]], <16 x i32> [[TMP105]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 18, i32 poison, i32 19, i32 poison, i32 12, i32 poison, i32 14, i32 15>
; THR15-NEXT: [[TMP107:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; THR15-NEXT: [[TMP108:%.*]] = shufflevector <16 x i32> [[TMP115]], <16 x i32> [[TMP107]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 18, i32 10, i32 19, i32 12, i32 16, i32 14, i32 15>
; THR15-NEXT: [[TMP109:%.*]] = lshr <16 x i32> [[TMP108]], splat (i32 15)
; THR15-NEXT: [[TMP110:%.*]] = and <16 x i32> [[TMP109]], splat (i32 65537)
; THR15-NEXT: [[TMP111:%.*]] = mul <16 x i32> [[TMP110]], splat (i32 65535)
; THR15-NEXT: [[TMP112:%.*]] = add <16 x i32> [[TMP111]], [[TMP97]]
; THR15-NEXT: [[TMP113:%.*]] = xor <16 x i32> [[TMP112]], [[TMP108]]
; THR15-NEXT: [[TMP114:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP113]])
; THR15-NEXT: ret i32 [[TMP114]]
;
; UNALIGNED_VEC_MEM-LABEL: define i32 @test(
; UNALIGNED_VEC_MEM-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
; UNALIGNED_VEC_MEM-NEXT: entry:
; UNALIGNED_VEC_MEM-NEXT: [[TMP54:%.*]] = load i8, ptr [[PIX1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV:%.*]] = zext i8 [[TMP54]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[TMP58:%.*]] = load i8, ptr [[PIX2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV2:%.*]] = zext i8 [[TMP58]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB:%.*]] = sub i32 [[CONV]], [[CONV2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV4:%.*]] = zext i8 [[TMP2]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX5]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV6:%.*]] = zext i8 [[TMP3]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB7:%.*]] = sub i32 [[CONV4]], [[CONV6]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL:%.*]] = shl i32 [[SUB7]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[SUB]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8:%.*]] = getelementptr i8, ptr [[PIX1]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP4:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV9:%.*]] = zext i8 [[TMP4]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10:%.*]] = getelementptr i8, ptr [[PIX2]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP5:%.*]] = load i8, ptr [[ARRAYIDX10]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV11:%.*]] = zext i8 [[TMP5]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB12:%.*]] = sub i32 [[CONV9]], [[CONV11]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX13:%.*]] = getelementptr i8, ptr [[PIX1]], i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP6:%.*]] = load i8, ptr [[ARRAYIDX13]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV14:%.*]] = zext i8 [[TMP6]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[PIX2]], i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP7:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV16:%.*]] = zext i8 [[TMP7]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB17:%.*]] = sub i32 [[CONV14]], [[CONV16]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL18:%.*]] = shl i32 [[SUB17]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD19:%.*]] = add i32 [[SHL18]], [[SUB12]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20:%.*]] = getelementptr i8, ptr [[PIX1]], i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP8:%.*]] = load i8, ptr [[ARRAYIDX20]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV21:%.*]] = zext i8 [[TMP8]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22:%.*]] = getelementptr i8, ptr [[PIX2]], i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP9:%.*]] = load i8, ptr [[ARRAYIDX22]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV23:%.*]] = zext i8 [[TMP9]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB24:%.*]] = sub i32 [[CONV21]], [[CONV23]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX25:%.*]] = getelementptr i8, ptr [[PIX1]], i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP10:%.*]] = load i8, ptr [[ARRAYIDX25]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV26:%.*]] = zext i8 [[TMP10]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27:%.*]] = getelementptr i8, ptr [[PIX2]], i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP11:%.*]] = load i8, ptr [[ARRAYIDX27]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV28:%.*]] = zext i8 [[TMP11]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB29:%.*]] = sub i32 [[CONV26]], [[CONV28]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL30:%.*]] = shl i32 [[SUB29]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD31:%.*]] = add i32 [[SHL30]], [[SUB24]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32:%.*]] = getelementptr i8, ptr [[PIX1]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP12:%.*]] = load i8, ptr [[ARRAYIDX32]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV33:%.*]] = zext i8 [[TMP12]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34:%.*]] = getelementptr i8, ptr [[PIX2]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP13:%.*]] = load i8, ptr [[ARRAYIDX34]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV35:%.*]] = zext i8 [[TMP13]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB36:%.*]] = sub i32 [[CONV33]], [[CONV35]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX37:%.*]] = getelementptr i8, ptr [[PIX1]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX37]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV38:%.*]] = zext i8 [[TMP14]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39:%.*]] = getelementptr i8, ptr [[PIX2]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP15:%.*]] = load i8, ptr [[ARRAYIDX39]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV40:%.*]] = zext i8 [[TMP15]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB41:%.*]] = sub i32 [[CONV38]], [[CONV40]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL42:%.*]] = shl i32 [[SUB41]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD43:%.*]] = add i32 [[SHL42]], [[SUB36]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD44:%.*]] = add i32 [[ADD19]], [[ADD]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB45:%.*]] = sub i32 [[ADD]], [[ADD19]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD46:%.*]] = add i32 [[ADD43]], [[ADD31]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB47:%.*]] = sub i32 [[ADD31]], [[ADD43]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD48:%.*]] = add i32 [[ADD46]], [[ADD44]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB51:%.*]] = sub i32 [[ADD44]], [[ADD46]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD55:%.*]] = add i32 [[SUB47]], [[SUB45]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59:%.*]] = sub i32 [[SUB45]], [[SUB47]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP16:%.*]] = load i8, ptr [[ADD_PTR3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV_1:%.*]] = zext i8 [[TMP16]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[TMP17:%.*]] = load i8, ptr [[ADD_PTR644]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV2_1:%.*]] = zext i8 [[TMP17]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB_1:%.*]] = sub i32 [[CONV_1]], [[CONV2_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP18:%.*]] = load i8, ptr [[ARRAYIDX3_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV4_1:%.*]] = zext i8 [[TMP18]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP19:%.*]] = load i8, ptr [[ARRAYIDX5_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV6_1:%.*]] = zext i8 [[TMP19]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB7_1:%.*]] = sub i32 [[CONV4_1]], [[CONV6_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL_1:%.*]] = shl i32 [[SUB7_1]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD_1:%.*]] = add i32 [[SHL_1]], [[SUB_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX8_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV9_1:%.*]] = zext i8 [[TMP20]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP21:%.*]] = load i8, ptr [[ARRAYIDX10_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV11_1:%.*]] = zext i8 [[TMP21]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB12_1:%.*]] = sub i32 [[CONV9_1]], [[CONV11_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX13_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP22:%.*]] = load i8, ptr [[ARRAYIDX13_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV14_1:%.*]] = zext i8 [[TMP22]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP23:%.*]] = load i8, ptr [[ARRAYIDX15_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV16_1:%.*]] = zext i8 [[TMP23]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB17_1:%.*]] = sub i32 [[CONV14_1]], [[CONV16_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL18_1:%.*]] = shl i32 [[SUB17_1]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD19_1:%.*]] = add i32 [[SHL18_1]], [[SUB12_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP24:%.*]] = load i8, ptr [[ARRAYIDX20_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV21_1:%.*]] = zext i8 [[TMP24]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP25:%.*]] = load i8, ptr [[ARRAYIDX22_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV23_1:%.*]] = zext i8 [[TMP25]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB24_1:%.*]] = sub i32 [[CONV21_1]], [[CONV23_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX25_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP26:%.*]] = load i8, ptr [[ARRAYIDX25_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV26_1:%.*]] = zext i8 [[TMP26]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP27:%.*]] = load i8, ptr [[ARRAYIDX27_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV28_1:%.*]] = zext i8 [[TMP27]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB29_1:%.*]] = sub i32 [[CONV26_1]], [[CONV28_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL30_1:%.*]] = shl i32 [[SUB29_1]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD31_1:%.*]] = add i32 [[SHL30_1]], [[SUB24_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP28:%.*]] = load i8, ptr [[ARRAYIDX32_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV33_1:%.*]] = zext i8 [[TMP28]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP29:%.*]] = load i8, ptr [[ARRAYIDX34_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV35_1:%.*]] = zext i8 [[TMP29]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB36_1:%.*]] = sub i32 [[CONV33_1]], [[CONV35_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX37_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP30:%.*]] = load i8, ptr [[ARRAYIDX37_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV38_1:%.*]] = zext i8 [[TMP30]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP31:%.*]] = load i8, ptr [[ARRAYIDX39_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV40_1:%.*]] = zext i8 [[TMP31]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB41_1:%.*]] = sub i32 [[CONV38_1]], [[CONV40_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL42_1:%.*]] = shl i32 [[SUB41_1]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD43_1:%.*]] = add i32 [[SHL42_1]], [[SUB36_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD44_1:%.*]] = add i32 [[ADD19_1]], [[ADD_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB45_1:%.*]] = sub i32 [[ADD_1]], [[ADD19_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD46_1:%.*]] = add i32 [[ADD43_1]], [[ADD31_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB47_1:%.*]] = sub i32 [[ADD31_1]], [[ADD43_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD48_1:%.*]] = add i32 [[ADD46_1]], [[ADD44_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB51_1:%.*]] = sub i32 [[ADD44_1]], [[ADD46_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD55_1:%.*]] = add i32 [[SUB47_1]], [[SUB45_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59_1:%.*]] = sub i32 [[SUB45_1]], [[SUB47_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP32:%.*]] = load i8, ptr [[ADD_PTR_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV_2:%.*]] = zext i8 [[TMP32]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[TMP33:%.*]] = load i8, ptr [[ADD_PTR64_1]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV2_2:%.*]] = zext i8 [[TMP33]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB_2:%.*]] = sub i32 [[CONV_2]], [[CONV2_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP34:%.*]] = load i8, ptr [[ARRAYIDX3_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV4_2:%.*]] = zext i8 [[TMP34]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP35:%.*]] = load i8, ptr [[ARRAYIDX5_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV6_2:%.*]] = zext i8 [[TMP35]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB7_2:%.*]] = sub i32 [[CONV4_2]], [[CONV6_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL_2:%.*]] = shl i32 [[SUB7_2]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD_2:%.*]] = add i32 [[SHL_2]], [[SUB_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP36:%.*]] = load i8, ptr [[ARRAYIDX8_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV9_2:%.*]] = zext i8 [[TMP36]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP37:%.*]] = load i8, ptr [[ARRAYIDX10_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV11_2:%.*]] = zext i8 [[TMP37]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB12_2:%.*]] = sub i32 [[CONV9_2]], [[CONV11_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX13_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP38:%.*]] = load i8, ptr [[ARRAYIDX13_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV14_2:%.*]] = zext i8 [[TMP38]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP39:%.*]] = load i8, ptr [[ARRAYIDX15_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV16_2:%.*]] = zext i8 [[TMP39]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB17_2:%.*]] = sub i32 [[CONV14_2]], [[CONV16_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL18_2:%.*]] = shl i32 [[SUB17_2]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD19_2:%.*]] = add i32 [[SHL18_2]], [[SUB12_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX20_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV21_2:%.*]] = zext i8 [[TMP40]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP41:%.*]] = load i8, ptr [[ARRAYIDX22_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV23_2:%.*]] = zext i8 [[TMP41]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB24_2:%.*]] = sub i32 [[CONV21_2]], [[CONV23_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX25_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP42:%.*]] = load i8, ptr [[ARRAYIDX25_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV26_2:%.*]] = zext i8 [[TMP42]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP43:%.*]] = load i8, ptr [[ARRAYIDX27_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV28_2:%.*]] = zext i8 [[TMP43]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB29_2:%.*]] = sub i32 [[CONV26_2]], [[CONV28_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL30_2:%.*]] = shl i32 [[SUB29_2]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD31_2:%.*]] = add i32 [[SHL30_2]], [[SUB24_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP44:%.*]] = load i8, ptr [[ARRAYIDX32_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV33_2:%.*]] = zext i8 [[TMP44]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP45:%.*]] = load i8, ptr [[ARRAYIDX34_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV35_2:%.*]] = zext i8 [[TMP45]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB36_2:%.*]] = sub i32 [[CONV33_2]], [[CONV35_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX37_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP46:%.*]] = load i8, ptr [[ARRAYIDX37_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV38_2:%.*]] = zext i8 [[TMP46]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP47:%.*]] = load i8, ptr [[ARRAYIDX39_2]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV40_2:%.*]] = zext i8 [[TMP47]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB41_2:%.*]] = sub i32 [[CONV38_2]], [[CONV40_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL42_2:%.*]] = shl i32 [[SUB41_2]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD43_2:%.*]] = add i32 [[SHL42_2]], [[SUB36_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD44_2:%.*]] = add i32 [[ADD19_2]], [[ADD_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB45_2:%.*]] = sub i32 [[ADD_2]], [[ADD19_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD46_2:%.*]] = add i32 [[ADD43_2]], [[ADD31_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB47_2:%.*]] = sub i32 [[ADD31_2]], [[ADD43_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD48_2:%.*]] = add i32 [[ADD46_2]], [[ADD44_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB51_2:%.*]] = sub i32 [[ADD44_2]], [[ADD46_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD55_2:%.*]] = add i32 [[SUB47_2]], [[SUB45_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59_2:%.*]] = sub i32 [[SUB45_2]], [[SUB47_2]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP48:%.*]] = load i8, ptr null, align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV_3:%.*]] = zext i8 [[TMP48]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[TMP49:%.*]] = load i8, ptr null, align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV2_3:%.*]] = zext i8 [[TMP49]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB_3:%.*]] = sub i32 [[CONV_3]], [[CONV2_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP50:%.*]] = load i8, ptr [[ARRAYIDX5_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV4_3:%.*]] = zext i8 [[TMP50]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_4:%.*]] = getelementptr i8, ptr null, i64 4
; UNALIGNED_VEC_MEM-NEXT: [[TMP51:%.*]] = load i8, ptr [[ARRAYIDX5_4]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV6_3:%.*]] = zext i8 [[TMP51]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB7_3:%.*]] = sub i32 [[CONV4_3]], [[CONV6_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL_3:%.*]] = shl i32 [[SUB7_3]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD_3:%.*]] = add i32 [[SHL_3]], [[SUB_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX8_3:%.*]] = getelementptr i8, ptr null, i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP52:%.*]] = load i8, ptr [[ARRAYIDX8_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV9_3:%.*]] = zext i8 [[TMP52]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX10_3:%.*]] = getelementptr i8, ptr null, i64 1
; UNALIGNED_VEC_MEM-NEXT: [[TMP53:%.*]] = load i8, ptr [[ARRAYIDX10_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV11_3:%.*]] = zext i8 [[TMP53]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB12_3:%.*]] = sub i32 [[CONV9_3]], [[CONV11_3]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV14_3:%.*]] = zext i8 [[TMP0]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX15_3:%.*]] = getelementptr i8, ptr null, i64 5
; UNALIGNED_VEC_MEM-NEXT: [[TMP55:%.*]] = load i8, ptr [[ARRAYIDX15_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV16_3:%.*]] = zext i8 [[TMP55]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB17_3:%.*]] = sub i32 [[CONV14_3]], [[CONV16_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL18_3:%.*]] = shl i32 [[SUB17_3]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD19_3:%.*]] = add i32 [[SHL18_3]], [[SUB12_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX20_3:%.*]] = getelementptr i8, ptr null, i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP56:%.*]] = load i8, ptr [[ARRAYIDX20_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV21_3:%.*]] = zext i8 [[TMP56]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX22_3:%.*]] = getelementptr i8, ptr null, i64 2
; UNALIGNED_VEC_MEM-NEXT: [[TMP57:%.*]] = load i8, ptr [[ARRAYIDX22_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV23_3:%.*]] = zext i8 [[TMP57]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB24_3:%.*]] = sub i32 [[CONV21_3]], [[CONV23_3]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP1:%.*]] = load i8, ptr null, align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV26_3:%.*]] = zext i8 [[TMP1]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX27_3:%.*]] = getelementptr i8, ptr null, i64 6
; UNALIGNED_VEC_MEM-NEXT: [[TMP59:%.*]] = load i8, ptr [[ARRAYIDX27_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV28_3:%.*]] = zext i8 [[TMP59]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB29_3:%.*]] = sub i32 [[CONV26_3]], [[CONV28_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL30_3:%.*]] = shl i32 [[SUB29_3]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD31_3:%.*]] = add i32 [[SHL30_3]], [[SUB24_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX32_3:%.*]] = getelementptr i8, ptr null, i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP60:%.*]] = load i8, ptr [[ARRAYIDX32_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV33_3:%.*]] = zext i8 [[TMP60]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX34_3:%.*]] = getelementptr i8, ptr null, i64 3
; UNALIGNED_VEC_MEM-NEXT: [[TMP61:%.*]] = load i8, ptr [[ARRAYIDX34_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV35_3:%.*]] = zext i8 [[TMP61]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB36_3:%.*]] = sub i32 [[CONV33_3]], [[CONV35_3]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP62:%.*]] = load i8, ptr null, align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV38_3:%.*]] = zext i8 [[TMP62]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX39_3:%.*]] = getelementptr i8, ptr null, i64 7
; UNALIGNED_VEC_MEM-NEXT: [[TMP63:%.*]] = load i8, ptr [[ARRAYIDX39_3]], align 1
; UNALIGNED_VEC_MEM-NEXT: [[CONV40_3:%.*]] = zext i8 [[TMP63]] to i32
; UNALIGNED_VEC_MEM-NEXT: [[SUB41_3:%.*]] = sub i32 [[CONV38_3]], [[CONV40_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SHL42_3:%.*]] = shl i32 [[SUB41_3]], 16
; UNALIGNED_VEC_MEM-NEXT: [[ADD43_3:%.*]] = add i32 [[SHL42_3]], [[SUB36_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD44_3:%.*]] = add i32 [[ADD19_3]], [[ADD_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB45_3:%.*]] = sub i32 [[ADD_3]], [[ADD19_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD46_3:%.*]] = add i32 [[ADD43_3]], [[ADD31_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB47_3:%.*]] = sub i32 [[ADD31_3]], [[ADD43_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD48_3:%.*]] = add i32 [[ADD46_3]], [[ADD44_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB51_3:%.*]] = sub i32 [[ADD44_3]], [[ADD46_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD55_3:%.*]] = add i32 [[SUB47_3]], [[SUB45_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB59_3:%.*]] = sub i32 [[SUB45_3]], [[SUB47_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD78:%.*]] = add i32 [[ADD48_1]], [[ADD48]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB86:%.*]] = sub i32 [[ADD48]], [[ADD48_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD94:%.*]] = add i32 [[ADD48_3]], [[ADD48_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB102:%.*]] = sub i32 [[ADD48_2]], [[ADD48_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD103:%.*]] = add i32 [[ADD94]], [[ADD78]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB104:%.*]] = sub i32 [[ADD78]], [[ADD94]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD105:%.*]] = add i32 [[SUB102]], [[SUB86]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB106:%.*]] = sub i32 [[SUB86]], [[SUB102]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I:%.*]] = lshr i32 [[CONV_3]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I:%.*]] = and i32 [[SHR_I]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I:%.*]] = mul i32 [[AND_I]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I:%.*]] = add i32 [[MUL_I]], [[ADD103]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I:%.*]] = xor i32 [[ADD_I]], [[CONV_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49:%.*]] = lshr i32 [[ADD46_2]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I50:%.*]] = and i32 [[SHR_I49]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51:%.*]] = mul i32 [[AND_I50]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52:%.*]] = add i32 [[MUL_I51]], [[ADD105]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53:%.*]] = xor i32 [[ADD_I52]], [[ADD46_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54:%.*]] = lshr i32 [[ADD46_1]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I55:%.*]] = and i32 [[SHR_I54]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56:%.*]] = mul i32 [[AND_I55]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57:%.*]] = add i32 [[MUL_I56]], [[SUB104]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58:%.*]] = xor i32 [[ADD_I57]], [[ADD46_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59:%.*]] = lshr i32 [[ADD46]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I60:%.*]] = and i32 [[SHR_I59]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61:%.*]] = mul i32 [[AND_I60]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62:%.*]] = add i32 [[MUL_I61]], [[SUB106]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63:%.*]] = xor i32 [[ADD_I62]], [[ADD46]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD110:%.*]] = add i32 [[XOR_I53]], [[XOR_I]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD112:%.*]] = add i32 [[ADD110]], [[XOR_I58]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD113:%.*]] = add i32 [[ADD112]], [[XOR_I63]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD78_1:%.*]] = add i32 [[ADD55_1]], [[ADD55]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB86_1:%.*]] = sub i32 [[ADD55]], [[ADD55_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD94_1:%.*]] = add i32 [[ADD55_3]], [[ADD55_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB102_1:%.*]] = sub i32 [[ADD55_2]], [[ADD55_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD103_1:%.*]] = add i32 [[ADD94_1]], [[ADD78_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB104_1:%.*]] = sub i32 [[ADD78_1]], [[ADD94_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD105_1:%.*]] = add i32 [[SUB102_1]], [[SUB86_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB106_1:%.*]] = sub i32 [[SUB86_1]], [[SUB102_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I_1:%.*]] = lshr i32 [[CONV9_2]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I_1:%.*]] = and i32 [[SHR_I_1]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I_1:%.*]] = mul i32 [[AND_I_1]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I_1:%.*]] = add i32 [[MUL_I_1]], [[ADD103_1]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I_1:%.*]] = xor i32 [[ADD_I_1]], [[CONV9_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49_1:%.*]] = lshr i32 [[CONV_2]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I50_1:%.*]] = and i32 [[SHR_I49_1]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51_1:%.*]] = mul i32 [[AND_I50_1]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52_1:%.*]] = add i32 [[MUL_I51_1]], [[ADD105_1]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53_1:%.*]] = xor i32 [[ADD_I52_1]], [[CONV_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54_1:%.*]] = lshr i32 [[SUB47_1]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I55_1:%.*]] = and i32 [[SHR_I54_1]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56_1:%.*]] = mul i32 [[AND_I55_1]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57_1:%.*]] = add i32 [[MUL_I56_1]], [[SUB104_1]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58_1:%.*]] = xor i32 [[ADD_I57_1]], [[SUB47_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59_1:%.*]] = lshr i32 [[SUB47]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I60_1:%.*]] = and i32 [[SHR_I59_1]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61_1:%.*]] = mul i32 [[AND_I60_1]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62_1:%.*]] = add i32 [[MUL_I61_1]], [[SUB106_1]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63_1:%.*]] = xor i32 [[ADD_I62_1]], [[SUB47]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD108_1:%.*]] = add i32 [[XOR_I53_1]], [[ADD113]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD110_1:%.*]] = add i32 [[ADD108_1]], [[XOR_I_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD112_1:%.*]] = add i32 [[ADD110_1]], [[XOR_I58_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD113_1:%.*]] = add i32 [[ADD112_1]], [[XOR_I63_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD78_2:%.*]] = add i32 [[SUB51_1]], [[SUB51]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB86_2:%.*]] = sub i32 [[SUB51]], [[SUB51_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD94_2:%.*]] = add i32 [[SUB51_3]], [[SUB51_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB102_2:%.*]] = sub i32 [[SUB51_2]], [[SUB51_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD103_2:%.*]] = add i32 [[ADD94_2]], [[ADD78_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB104_2:%.*]] = sub i32 [[ADD78_2]], [[ADD94_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD105_2:%.*]] = add i32 [[SUB102_2]], [[SUB86_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB106_2:%.*]] = sub i32 [[SUB86_2]], [[SUB102_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I_2:%.*]] = lshr i32 [[CONV9_1]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I_2:%.*]] = and i32 [[SHR_I_2]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I_2:%.*]] = mul i32 [[AND_I_2]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I_2:%.*]] = add i32 [[MUL_I_2]], [[ADD103_2]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I_2:%.*]] = xor i32 [[ADD_I_2]], [[CONV9_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49_2:%.*]] = lshr i32 [[CONV_1]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I50_2:%.*]] = and i32 [[SHR_I49_2]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51_2:%.*]] = mul i32 [[AND_I50_2]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52_2:%.*]] = add i32 [[MUL_I51_2]], [[ADD105_2]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53_2:%.*]] = xor i32 [[ADD_I52_2]], [[CONV_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54_2:%.*]] = lshr i32 [[CONV21_1]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I55_2:%.*]] = and i32 [[SHR_I54_2]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56_2:%.*]] = mul i32 [[AND_I55_2]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57_2:%.*]] = add i32 [[MUL_I56_2]], [[SUB104_2]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58_2:%.*]] = xor i32 [[ADD_I57_2]], [[CONV21_1]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59_2:%.*]] = lshr i32 [[ADD44]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I60_2:%.*]] = and i32 [[SHR_I59_2]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61_2:%.*]] = mul i32 [[AND_I60_2]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62_2:%.*]] = add i32 [[MUL_I61_2]], [[SUB106_2]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63_2:%.*]] = xor i32 [[ADD_I62_2]], [[ADD44]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD108_2:%.*]] = add i32 [[XOR_I53_2]], [[ADD113_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD110_2:%.*]] = add i32 [[ADD108_2]], [[XOR_I_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD112_2:%.*]] = add i32 [[ADD110_2]], [[XOR_I58_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD113_2:%.*]] = add i32 [[ADD112_2]], [[XOR_I63_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD78_3:%.*]] = add i32 [[SUB59_1]], [[SUB59]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB86_3:%.*]] = sub i32 [[SUB59]], [[SUB59_1]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD94_3:%.*]] = add i32 [[SUB59_3]], [[SUB59_2]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB102_3:%.*]] = sub i32 [[SUB59_2]], [[SUB59_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD103_3:%.*]] = add i32 [[ADD94_3]], [[ADD78_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB104_3:%.*]] = sub i32 [[ADD78_3]], [[ADD94_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD105_3:%.*]] = add i32 [[SUB102_3]], [[SUB86_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SUB106_3:%.*]] = sub i32 [[SUB86_3]], [[SUB102_3]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I_3:%.*]] = lshr i32 [[CONV9]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I_3:%.*]] = and i32 [[SHR_I_3]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I_3:%.*]] = mul i32 [[AND_I_3]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I_3:%.*]] = add i32 [[MUL_I_3]], [[ADD103_3]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I_3:%.*]] = xor i32 [[ADD_I_3]], [[CONV9]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I49_3:%.*]] = lshr i32 [[CONV]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I50_3:%.*]] = and i32 [[SHR_I49_3]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I51_3:%.*]] = mul i32 [[AND_I50_3]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I52_3:%.*]] = add i32 [[MUL_I51_3]], [[ADD105_3]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I53_3:%.*]] = xor i32 [[ADD_I52_3]], [[CONV]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I54_3:%.*]] = lshr i32 [[CONV21]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I55_3:%.*]] = and i32 [[SHR_I54_3]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I56_3:%.*]] = mul i32 [[AND_I55_3]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I57_3:%.*]] = add i32 [[MUL_I56_3]], [[SUB104_3]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I58_3:%.*]] = xor i32 [[ADD_I57_3]], [[CONV21]]
; UNALIGNED_VEC_MEM-NEXT: [[SHR_I59_3:%.*]] = lshr i32 [[CONV33]], 15
; UNALIGNED_VEC_MEM-NEXT: [[AND_I60_3:%.*]] = and i32 [[SHR_I59_3]], 65537
; UNALIGNED_VEC_MEM-NEXT: [[MUL_I61_3:%.*]] = mul i32 [[AND_I60_3]], 65535
; UNALIGNED_VEC_MEM-NEXT: [[ADD_I62_3:%.*]] = add i32 [[MUL_I61_3]], [[SUB106_3]]
; UNALIGNED_VEC_MEM-NEXT: [[XOR_I63_3:%.*]] = xor i32 [[ADD_I62_3]], [[CONV33]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD108_3:%.*]] = add i32 [[XOR_I53_3]], [[ADD113_2]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD110_3:%.*]] = add i32 [[ADD108_3]], [[XOR_I_3]]
; UNALIGNED_VEC_MEM-NEXT: [[ADD112_3:%.*]] = add i32 [[ADD110_3]], [[XOR_I58_3]]
; UNALIGNED_VEC_MEM-NEXT: [[TMP117:%.*]] = add i32 [[ADD112_3]], [[XOR_I63_3]]
; UNALIGNED_VEC_MEM-NEXT: ret i32 [[TMP117]]
;
entry:
%0 = load i8, ptr %pix1, align 1
%conv = zext i8 %0 to i32
%1 = load i8, ptr %pix2, align 1
%conv2 = zext i8 %1 to i32
%sub = sub i32 %conv, %conv2
%arrayidx3 = getelementptr i8, ptr %pix1, i64 4
%2 = load i8, ptr %arrayidx3, align 1
%conv4 = zext i8 %2 to i32
%arrayidx5 = getelementptr i8, ptr %pix2, i64 4
%3 = load i8, ptr %arrayidx5, align 1
%conv6 = zext i8 %3 to i32
%sub7 = sub i32 %conv4, %conv6
%shl = shl i32 %sub7, 16
%add = add i32 %shl, %sub
%arrayidx8 = getelementptr i8, ptr %pix1, i64 1
%4 = load i8, ptr %arrayidx8, align 1
%conv9 = zext i8 %4 to i32
%arrayidx10 = getelementptr i8, ptr %pix2, i64 1
%5 = load i8, ptr %arrayidx10, align 1
%conv11 = zext i8 %5 to i32
%sub12 = sub i32 %conv9, %conv11
%arrayidx13 = getelementptr i8, ptr %pix1, i64 5
%6 = load i8, ptr %arrayidx13, align 1
%conv14 = zext i8 %6 to i32
%arrayidx15 = getelementptr i8, ptr %pix2, i64 5
%7 = load i8, ptr %arrayidx15, align 1
%conv16 = zext i8 %7 to i32
%sub17 = sub i32 %conv14, %conv16
%shl18 = shl i32 %sub17, 16
%add19 = add i32 %shl18, %sub12
%arrayidx20 = getelementptr i8, ptr %pix1, i64 2
%8 = load i8, ptr %arrayidx20, align 1
%conv21 = zext i8 %8 to i32
%arrayidx22 = getelementptr i8, ptr %pix2, i64 2
%9 = load i8, ptr %arrayidx22, align 1
%conv23 = zext i8 %9 to i32
%sub24 = sub i32 %conv21, %conv23
%arrayidx25 = getelementptr i8, ptr %pix1, i64 6
%10 = load i8, ptr %arrayidx25, align 1
%conv26 = zext i8 %10 to i32
%arrayidx27 = getelementptr i8, ptr %pix2, i64 6
%11 = load i8, ptr %arrayidx27, align 1
%conv28 = zext i8 %11 to i32
%sub29 = sub i32 %conv26, %conv28
%shl30 = shl i32 %sub29, 16
%add31 = add i32 %shl30, %sub24
%arrayidx32 = getelementptr i8, ptr %pix1, i64 3
%12 = load i8, ptr %arrayidx32, align 1
%conv33 = zext i8 %12 to i32
%arrayidx34 = getelementptr i8, ptr %pix2, i64 3
%13 = load i8, ptr %arrayidx34, align 1
%conv35 = zext i8 %13 to i32
%sub36 = sub i32 %conv33, %conv35
%arrayidx37 = getelementptr i8, ptr %pix1, i64 7
%14 = load i8, ptr %arrayidx37, align 1
%conv38 = zext i8 %14 to i32
%arrayidx39 = getelementptr i8, ptr %pix2, i64 7
%15 = load i8, ptr %arrayidx39, align 1
%conv40 = zext i8 %15 to i32
%sub41 = sub i32 %conv38, %conv40
%shl42 = shl i32 %sub41, 16
%add43 = add i32 %shl42, %sub36
%add44 = add i32 %add19, %add
%sub45 = sub i32 %add, %add19
%add46 = add i32 %add43, %add31
%sub47 = sub i32 %add31, %add43
%add48 = add i32 %add46, %add44
%sub51 = sub i32 %add44, %add46
%add55 = add i32 %sub47, %sub45
%sub59 = sub i32 %sub45, %sub47
%add.ptr3 = getelementptr i8, ptr %pix1, i64 %idx.ext
%add.ptr644 = getelementptr i8, ptr %pix2, i64 %idx.ext63
%16 = load i8, ptr %add.ptr3, align 1
%conv.1 = zext i8 %16 to i32
%17 = load i8, ptr %add.ptr644, align 1
%conv2.1 = zext i8 %17 to i32
%sub.1 = sub i32 %conv.1, %conv2.1
%arrayidx3.1 = getelementptr i8, ptr %add.ptr3, i64 4
%18 = load i8, ptr %arrayidx3.1, align 1
%conv4.1 = zext i8 %18 to i32
%arrayidx5.1 = getelementptr i8, ptr %add.ptr644, i64 4
%19 = load i8, ptr %arrayidx5.1, align 1
%conv6.1 = zext i8 %19 to i32
%sub7.1 = sub i32 %conv4.1, %conv6.1
%shl.1 = shl i32 %sub7.1, 16
%add.1 = add i32 %shl.1, %sub.1
%arrayidx8.1 = getelementptr i8, ptr %add.ptr3, i64 1
%20 = load i8, ptr %arrayidx8.1, align 1
%conv9.1 = zext i8 %20 to i32
%arrayidx10.1 = getelementptr i8, ptr %add.ptr644, i64 1
%21 = load i8, ptr %arrayidx10.1, align 1
%conv11.1 = zext i8 %21 to i32
%sub12.1 = sub i32 %conv9.1, %conv11.1
%arrayidx13.1 = getelementptr i8, ptr %add.ptr3, i64 5
%22 = load i8, ptr %arrayidx13.1, align 1
%conv14.1 = zext i8 %22 to i32
%arrayidx15.1 = getelementptr i8, ptr %add.ptr644, i64 5
%23 = load i8, ptr %arrayidx15.1, align 1
%conv16.1 = zext i8 %23 to i32
%sub17.1 = sub i32 %conv14.1, %conv16.1
%shl18.1 = shl i32 %sub17.1, 16
%add19.1 = add i32 %shl18.1, %sub12.1
%arrayidx20.1 = getelementptr i8, ptr %add.ptr3, i64 2
%24 = load i8, ptr %arrayidx20.1, align 1
%conv21.1 = zext i8 %24 to i32
%arrayidx22.1 = getelementptr i8, ptr %add.ptr644, i64 2
%25 = load i8, ptr %arrayidx22.1, align 1
%conv23.1 = zext i8 %25 to i32
%sub24.1 = sub i32 %conv21.1, %conv23.1
%arrayidx25.1 = getelementptr i8, ptr %add.ptr3, i64 6
%26 = load i8, ptr %arrayidx25.1, align 1
%conv26.1 = zext i8 %26 to i32
%arrayidx27.1 = getelementptr i8, ptr %add.ptr644, i64 6
%27 = load i8, ptr %arrayidx27.1, align 1
%conv28.1 = zext i8 %27 to i32
%sub29.1 = sub i32 %conv26.1, %conv28.1
%shl30.1 = shl i32 %sub29.1, 16
%add31.1 = add i32 %shl30.1, %sub24.1
%arrayidx32.1 = getelementptr i8, ptr %add.ptr3, i64 3
%28 = load i8, ptr %arrayidx32.1, align 1
%conv33.1 = zext i8 %28 to i32
%arrayidx34.1 = getelementptr i8, ptr %add.ptr644, i64 3
%29 = load i8, ptr %arrayidx34.1, align 1
%conv35.1 = zext i8 %29 to i32
%sub36.1 = sub i32 %conv33.1, %conv35.1
%arrayidx37.1 = getelementptr i8, ptr %add.ptr3, i64 7
%30 = load i8, ptr %arrayidx37.1, align 1
%conv38.1 = zext i8 %30 to i32
%arrayidx39.1 = getelementptr i8, ptr %add.ptr644, i64 7
%31 = load i8, ptr %arrayidx39.1, align 1
%conv40.1 = zext i8 %31 to i32
%sub41.1 = sub i32 %conv38.1, %conv40.1
%shl42.1 = shl i32 %sub41.1, 16
%add43.1 = add i32 %shl42.1, %sub36.1
%add44.1 = add i32 %add19.1, %add.1
%sub45.1 = sub i32 %add.1, %add19.1
%add46.1 = add i32 %add43.1, %add31.1
%sub47.1 = sub i32 %add31.1, %add43.1
%add48.1 = add i32 %add46.1, %add44.1
%sub51.1 = sub i32 %add44.1, %add46.1
%add55.1 = add i32 %sub47.1, %sub45.1
%sub59.1 = sub i32 %sub45.1, %sub47.1
%add.ptr.1 = getelementptr i8, ptr %add.ptr, i64 %idx.ext
%add.ptr64.1 = getelementptr i8, ptr %add.ptr64, i64 %idx.ext63
%32 = load i8, ptr %add.ptr.1, align 1
%conv.2 = zext i8 %32 to i32
%33 = load i8, ptr %add.ptr64.1, align 1
%conv2.2 = zext i8 %33 to i32
%sub.2 = sub i32 %conv.2, %conv2.2
%arrayidx3.2 = getelementptr i8, ptr %add.ptr.1, i64 4
%34 = load i8, ptr %arrayidx3.2, align 1
%conv4.2 = zext i8 %34 to i32
%arrayidx5.2 = getelementptr i8, ptr %add.ptr64.1, i64 4
%35 = load i8, ptr %arrayidx5.2, align 1
%conv6.2 = zext i8 %35 to i32
%sub7.2 = sub i32 %conv4.2, %conv6.2
%shl.2 = shl i32 %sub7.2, 16
%add.2 = add i32 %shl.2, %sub.2
%arrayidx8.2 = getelementptr i8, ptr %add.ptr.1, i64 1
%36 = load i8, ptr %arrayidx8.2, align 1
%conv9.2 = zext i8 %36 to i32
%arrayidx10.2 = getelementptr i8, ptr %add.ptr64.1, i64 1
%37 = load i8, ptr %arrayidx10.2, align 1
%conv11.2 = zext i8 %37 to i32
%sub12.2 = sub i32 %conv9.2, %conv11.2
%arrayidx13.2 = getelementptr i8, ptr %add.ptr.1, i64 5
%38 = load i8, ptr %arrayidx13.2, align 1
%conv14.2 = zext i8 %38 to i32
%arrayidx15.2 = getelementptr i8, ptr %add.ptr64.1, i64 5
%39 = load i8, ptr %arrayidx15.2, align 1
%conv16.2 = zext i8 %39 to i32
%sub17.2 = sub i32 %conv14.2, %conv16.2
%shl18.2 = shl i32 %sub17.2, 16
%add19.2 = add i32 %shl18.2, %sub12.2
%arrayidx20.2 = getelementptr i8, ptr %add.ptr.1, i64 2
%40 = load i8, ptr %arrayidx20.2, align 1
%conv21.2 = zext i8 %40 to i32
%arrayidx22.2 = getelementptr i8, ptr %add.ptr64.1, i64 2
%41 = load i8, ptr %arrayidx22.2, align 1
%conv23.2 = zext i8 %41 to i32
%sub24.2 = sub i32 %conv21.2, %conv23.2
%arrayidx25.2 = getelementptr i8, ptr %add.ptr.1, i64 6
%42 = load i8, ptr %arrayidx25.2, align 1
%conv26.2 = zext i8 %42 to i32
%arrayidx27.2 = getelementptr i8, ptr %add.ptr64.1, i64 6
%43 = load i8, ptr %arrayidx27.2, align 1
%conv28.2 = zext i8 %43 to i32
%sub29.2 = sub i32 %conv26.2, %conv28.2
%shl30.2 = shl i32 %sub29.2, 16
%add31.2 = add i32 %shl30.2, %sub24.2
%arrayidx32.2 = getelementptr i8, ptr %add.ptr.1, i64 3
%44 = load i8, ptr %arrayidx32.2, align 1
%conv33.2 = zext i8 %44 to i32
%arrayidx34.2 = getelementptr i8, ptr %add.ptr64.1, i64 3
%45 = load i8, ptr %arrayidx34.2, align 1
%conv35.2 = zext i8 %45 to i32
%sub36.2 = sub i32 %conv33.2, %conv35.2
%arrayidx37.2 = getelementptr i8, ptr %add.ptr.1, i64 7
%46 = load i8, ptr %arrayidx37.2, align 1
%conv38.2 = zext i8 %46 to i32
%arrayidx39.2 = getelementptr i8, ptr %add.ptr64.1, i64 7
%47 = load i8, ptr %arrayidx39.2, align 1
%conv40.2 = zext i8 %47 to i32
%sub41.2 = sub i32 %conv38.2, %conv40.2
%shl42.2 = shl i32 %sub41.2, 16
%add43.2 = add i32 %shl42.2, %sub36.2
%add44.2 = add i32 %add19.2, %add.2
%sub45.2 = sub i32 %add.2, %add19.2
%add46.2 = add i32 %add43.2, %add31.2
%sub47.2 = sub i32 %add31.2, %add43.2
%add48.2 = add i32 %add46.2, %add44.2
%sub51.2 = sub i32 %add44.2, %add46.2
%add55.2 = add i32 %sub47.2, %sub45.2
%sub59.2 = sub i32 %sub45.2, %sub47.2
%48 = load i8, ptr null, align 1
%conv.3 = zext i8 %48 to i32
%49 = load i8, ptr null, align 1
%conv2.3 = zext i8 %49 to i32
%sub.3 = sub i32 %conv.3, %conv2.3
%arrayidx3.3 = getelementptr i8, ptr null, i64 4
%50 = load i8, ptr %arrayidx3.3, align 1
%conv4.3 = zext i8 %50 to i32
%arrayidx5.3 = getelementptr i8, ptr null, i64 4
%51 = load i8, ptr %arrayidx5.3, align 1
%conv6.3 = zext i8 %51 to i32
%sub7.3 = sub i32 %conv4.3, %conv6.3
%shl.3 = shl i32 %sub7.3, 16
%add.3 = add i32 %shl.3, %sub.3
%arrayidx8.3 = getelementptr i8, ptr null, i64 1
%52 = load i8, ptr %arrayidx8.3, align 1
%conv9.3 = zext i8 %52 to i32
%arrayidx10.3 = getelementptr i8, ptr null, i64 1
%53 = load i8, ptr %arrayidx10.3, align 1
%conv11.3 = zext i8 %53 to i32
%sub12.3 = sub i32 %conv9.3, %conv11.3
%54 = load i8, ptr null, align 1
%conv14.3 = zext i8 %54 to i32
%arrayidx15.3 = getelementptr i8, ptr null, i64 5
%55 = load i8, ptr %arrayidx15.3, align 1
%conv16.3 = zext i8 %55 to i32
%sub17.3 = sub i32 %conv14.3, %conv16.3
%shl18.3 = shl i32 %sub17.3, 16
%add19.3 = add i32 %shl18.3, %sub12.3
%arrayidx20.3 = getelementptr i8, ptr null, i64 2
%56 = load i8, ptr %arrayidx20.3, align 1
%conv21.3 = zext i8 %56 to i32
%arrayidx22.3 = getelementptr i8, ptr null, i64 2
%57 = load i8, ptr %arrayidx22.3, align 1
%conv23.3 = zext i8 %57 to i32
%sub24.3 = sub i32 %conv21.3, %conv23.3
%58 = load i8, ptr null, align 1
%conv26.3 = zext i8 %58 to i32
%arrayidx27.3 = getelementptr i8, ptr null, i64 6
%59 = load i8, ptr %arrayidx27.3, align 1
%conv28.3 = zext i8 %59 to i32
%sub29.3 = sub i32 %conv26.3, %conv28.3
%shl30.3 = shl i32 %sub29.3, 16
%add31.3 = add i32 %shl30.3, %sub24.3
%arrayidx32.3 = getelementptr i8, ptr null, i64 3
%60 = load i8, ptr %arrayidx32.3, align 1
%conv33.3 = zext i8 %60 to i32
%arrayidx34.3 = getelementptr i8, ptr null, i64 3
%61 = load i8, ptr %arrayidx34.3, align 1
%conv35.3 = zext i8 %61 to i32
%sub36.3 = sub i32 %conv33.3, %conv35.3
%62 = load i8, ptr null, align 1
%conv38.3 = zext i8 %62 to i32
%arrayidx39.3 = getelementptr i8, ptr null, i64 7
%63 = load i8, ptr %arrayidx39.3, align 1
%conv40.3 = zext i8 %63 to i32
%sub41.3 = sub i32 %conv38.3, %conv40.3
%shl42.3 = shl i32 %sub41.3, 16
%add43.3 = add i32 %shl42.3, %sub36.3
%add44.3 = add i32 %add19.3, %add.3
%sub45.3 = sub i32 %add.3, %add19.3
%add46.3 = add i32 %add43.3, %add31.3
%sub47.3 = sub i32 %add31.3, %add43.3
%add48.3 = add i32 %add46.3, %add44.3
%sub51.3 = sub i32 %add44.3, %add46.3
%add55.3 = add i32 %sub47.3, %sub45.3
%sub59.3 = sub i32 %sub45.3, %sub47.3
%add78 = add i32 %add48.1, %add48
%sub86 = sub i32 %add48, %add48.1
%add94 = add i32 %add48.3, %add48.2
%sub102 = sub i32 %add48.2, %add48.3
%add103 = add i32 %add94, %add78
%sub104 = sub i32 %add78, %add94
%add105 = add i32 %sub102, %sub86
%sub106 = sub i32 %sub86, %sub102
%shr.i = lshr i32 %conv.3, 15
%and.i = and i32 %shr.i, 65537
%mul.i = mul i32 %and.i, 65535
%add.i = add i32 %mul.i, %add103
%xor.i = xor i32 %add.i, %conv.3
%shr.i49 = lshr i32 %add46.2, 15
%and.i50 = and i32 %shr.i49, 65537
%mul.i51 = mul i32 %and.i50, 65535
%add.i52 = add i32 %mul.i51, %add105
%xor.i53 = xor i32 %add.i52, %add46.2
%shr.i54 = lshr i32 %add46.1, 15
%and.i55 = and i32 %shr.i54, 65537
%mul.i56 = mul i32 %and.i55, 65535
%add.i57 = add i32 %mul.i56, %sub104
%xor.i58 = xor i32 %add.i57, %add46.1
%shr.i59 = lshr i32 %add46, 15
%and.i60 = and i32 %shr.i59, 65537
%mul.i61 = mul i32 %and.i60, 65535
%add.i62 = add i32 %mul.i61, %sub106
%xor.i63 = xor i32 %add.i62, %add46
%add110 = add i32 %xor.i53, %xor.i
%add112 = add i32 %add110, %xor.i58
%add113 = add i32 %add112, %xor.i63
%add78.1 = add i32 %add55.1, %add55
%sub86.1 = sub i32 %add55, %add55.1
%add94.1 = add i32 %add55.3, %add55.2
%sub102.1 = sub i32 %add55.2, %add55.3
%add103.1 = add i32 %add94.1, %add78.1
%sub104.1 = sub i32 %add78.1, %add94.1
%add105.1 = add i32 %sub102.1, %sub86.1
%sub106.1 = sub i32 %sub86.1, %sub102.1
%shr.i.1 = lshr i32 %conv9.2, 15
%and.i.1 = and i32 %shr.i.1, 65537
%mul.i.1 = mul i32 %and.i.1, 65535
%add.i.1 = add i32 %mul.i.1, %add103.1
%xor.i.1 = xor i32 %add.i.1, %conv9.2
%shr.i49.1 = lshr i32 %conv.2, 15
%and.i50.1 = and i32 %shr.i49.1, 65537
%mul.i51.1 = mul i32 %and.i50.1, 65535
%add.i52.1 = add i32 %mul.i51.1, %add105.1
%xor.i53.1 = xor i32 %add.i52.1, %conv.2
%shr.i54.1 = lshr i32 %sub47.1, 15
%and.i55.1 = and i32 %shr.i54.1, 65537
%mul.i56.1 = mul i32 %and.i55.1, 65535
%add.i57.1 = add i32 %mul.i56.1, %sub104.1
%xor.i58.1 = xor i32 %add.i57.1, %sub47.1
%shr.i59.1 = lshr i32 %sub47, 15
%and.i60.1 = and i32 %shr.i59.1, 65537
%mul.i61.1 = mul i32 %and.i60.1, 65535
%add.i62.1 = add i32 %mul.i61.1, %sub106.1
%xor.i63.1 = xor i32 %add.i62.1, %sub47
%add108.1 = add i32 %xor.i53.1, %add113
%add110.1 = add i32 %add108.1, %xor.i.1
%add112.1 = add i32 %add110.1, %xor.i58.1
%add113.1 = add i32 %add112.1, %xor.i63.1
%add78.2 = add i32 %sub51.1, %sub51
%sub86.2 = sub i32 %sub51, %sub51.1
%add94.2 = add i32 %sub51.3, %sub51.2
%sub102.2 = sub i32 %sub51.2, %sub51.3
%add103.2 = add i32 %add94.2, %add78.2
%sub104.2 = sub i32 %add78.2, %add94.2
%add105.2 = add i32 %sub102.2, %sub86.2
%sub106.2 = sub i32 %sub86.2, %sub102.2
%shr.i.2 = lshr i32 %conv9.1, 15
%and.i.2 = and i32 %shr.i.2, 65537
%mul.i.2 = mul i32 %and.i.2, 65535
%add.i.2 = add i32 %mul.i.2, %add103.2
%xor.i.2 = xor i32 %add.i.2, %conv9.1
%shr.i49.2 = lshr i32 %conv.1, 15
%and.i50.2 = and i32 %shr.i49.2, 65537
%mul.i51.2 = mul i32 %and.i50.2, 65535
%add.i52.2 = add i32 %mul.i51.2, %add105.2
%xor.i53.2 = xor i32 %add.i52.2, %conv.1
%shr.i54.2 = lshr i32 %conv21.1, 15
%and.i55.2 = and i32 %shr.i54.2, 65537
%mul.i56.2 = mul i32 %and.i55.2, 65535
%add.i57.2 = add i32 %mul.i56.2, %sub104.2
%xor.i58.2 = xor i32 %add.i57.2, %conv21.1
%shr.i59.2 = lshr i32 %add44, 15
%and.i60.2 = and i32 %shr.i59.2, 65537
%mul.i61.2 = mul i32 %and.i60.2, 65535
%add.i62.2 = add i32 %mul.i61.2, %sub106.2
%xor.i63.2 = xor i32 %add.i62.2, %add44
%add108.2 = add i32 %xor.i53.2, %add113.1
%add110.2 = add i32 %add108.2, %xor.i.2
%add112.2 = add i32 %add110.2, %xor.i58.2
%add113.2 = add i32 %add112.2, %xor.i63.2
%add78.3 = add i32 %sub59.1, %sub59
%sub86.3 = sub i32 %sub59, %sub59.1
%add94.3 = add i32 %sub59.3, %sub59.2
%sub102.3 = sub i32 %sub59.2, %sub59.3
%add103.3 = add i32 %add94.3, %add78.3
%sub104.3 = sub i32 %add78.3, %add94.3
%add105.3 = add i32 %sub102.3, %sub86.3
%sub106.3 = sub i32 %sub86.3, %sub102.3
%shr.i.3 = lshr i32 %conv9, 15
%and.i.3 = and i32 %shr.i.3, 65537
%mul.i.3 = mul i32 %and.i.3, 65535
%add.i.3 = add i32 %mul.i.3, %add103.3
%xor.i.3 = xor i32 %add.i.3, %conv9
%shr.i49.3 = lshr i32 %conv, 15
%and.i50.3 = and i32 %shr.i49.3, 65537
%mul.i51.3 = mul i32 %and.i50.3, 65535
%add.i52.3 = add i32 %mul.i51.3, %add105.3
%xor.i53.3 = xor i32 %add.i52.3, %conv
%shr.i54.3 = lshr i32 %conv21, 15
%and.i55.3 = and i32 %shr.i54.3, 65537
%mul.i56.3 = mul i32 %and.i55.3, 65535
%add.i57.3 = add i32 %mul.i56.3, %sub104.3
%xor.i58.3 = xor i32 %add.i57.3, %conv21
%shr.i59.3 = lshr i32 %conv33, 15
%and.i60.3 = and i32 %shr.i59.3, 65537
%mul.i61.3 = mul i32 %and.i60.3, 65535
%add.i62.3 = add i32 %mul.i61.3, %sub106.3
%xor.i63.3 = xor i32 %add.i62.3, %conv33
%add108.3 = add i32 %xor.i53.3, %add113.2
%add110.3 = add i32 %add108.3, %xor.i.3
%add112.3 = add i32 %add110.3, %xor.i58.3
%add113.3 = add i32 %add112.3, %xor.i63.3
ret i32 %add113.3
}
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