972cd847ef
Remove xevm to llvm conversion pass from convert to llvm as it is a backend dependent conversion. And add legalization pattern for splitting large vector load that are eventually split into smaller vectors by shufflevector. shufflevector can be replaced with a smaller load in such case.
1067 lines
40 KiB
C++
1067 lines
40 KiB
C++
//===-- XeVMToLLVM.cpp - XeVM to LLVM dialect conversion --------*- C++ -*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/XeVMToLLVM/XeVMToLLVM.h"
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#include "mlir/Conversion/LLVMCommon/Pattern.h"
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#include "mlir/Dialect/LLVMIR/FunctionCallUtils.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/LLVMIR/XeVMDialect.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Support/LLVM.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/Types.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "llvm/ADT/TypeSwitch.h"
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTXEVMTOLLVMPASS
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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using namespace xevm;
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namespace {
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struct LLVMFuncAttributeOptions {
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bool isConvergent = false;
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bool isNoUnwind = false;
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bool isWillReturn = false;
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LLVM::MemoryEffectsAttr memEffectsAttr{};
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};
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static constexpr LLVMFuncAttributeOptions noUnwindAttrs = {
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false, true, false, {}};
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static constexpr LLVMFuncAttributeOptions noUnwindWillReturnAttrs = {
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false, true, true, {}};
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static constexpr LLVMFuncAttributeOptions convergentNoUnwindWillReturnAttrs = {
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true, true, true, {}};
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std::string getTypeMangling(Type ty, bool isUnsigned = false) {
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return TypeSwitch<Type, std::string>(ty)
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.Case([isUnsigned](VectorType ty) -> std::string {
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return "Dv" + std::to_string(ty.getNumElements()) + "_" +
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getTypeMangling(ty.getElementType(), isUnsigned);
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})
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.Case([](Float16Type) -> std::string { return "Dh"; })
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.Case([](Float32Type) -> std::string { return "f"; })
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.Case([](Float64Type) -> std::string { return "d"; })
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.Case([isUnsigned](IntegerType ty) -> std::string {
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switch (ty.getWidth()) {
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case 8:
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return isUnsigned ? "h" : "c";
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case 16:
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return isUnsigned ? "t" : "s";
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case 32:
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return isUnsigned ? "j" : "i";
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case 64:
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return isUnsigned ? "m" : "l";
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default:
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llvm_unreachable("unhandled integer type");
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}
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})
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.DefaultUnreachable("unhandled type for mangling");
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}
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std::string mangle(StringRef baseName, ArrayRef<Type> types,
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ArrayRef<bool> isUnsigned = {}) {
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assert((isUnsigned.empty() || isUnsigned.size() == types.size()) &&
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"Signedness info doesn't match");
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std::string s;
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llvm::raw_string_ostream os(s);
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llvm::SmallDenseMap<Type, unsigned> substitutions;
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os << "_Z" << baseName.size() << baseName;
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for (auto [idx, type] : llvm::enumerate(types)) {
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auto it = substitutions.find(type);
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if (it != substitutions.end()) {
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os << "S";
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// First substitution is `S_`, second is `S0_`, and so on.
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if (unsigned firstIdx = it->getSecond(); firstIdx > 0)
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os << firstIdx - 1;
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os << "_";
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} else {
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if (!type.isIntOrFloat())
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substitutions[type] = substitutions.size();
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os << getTypeMangling(type, isUnsigned.empty() ? false : isUnsigned[idx]);
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}
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}
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return os.str();
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}
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static int32_t getL1CacheControl(LoadCacheControl cc) {
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int32_t control = 0;
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switch (cc) {
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case LoadCacheControl::L1UC_L2UC_L3UC:
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case LoadCacheControl::L1UC_L2UC_L3C:
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case LoadCacheControl::L1UC_L2C_L3UC:
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case LoadCacheControl::L1UC_L2C_L3C:
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control = 1;
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break;
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case LoadCacheControl::L1C_L2UC_L3UC:
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case LoadCacheControl::L1C_L2UC_L3C:
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case LoadCacheControl::L1C_L2C_L3UC:
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case LoadCacheControl::L1C_L2C_L3C:
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control = 2;
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break;
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case LoadCacheControl::L1S_L2UC_L3UC:
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case LoadCacheControl::L1S_L2UC_L3C:
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case LoadCacheControl::L1S_L2C_L3UC:
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case LoadCacheControl::L1S_L2C_L3C:
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control = 3;
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break;
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case LoadCacheControl::INVALIDATE_READ:
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control = 4;
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break;
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}
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return control;
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}
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static int32_t getL1CacheControl(StoreCacheControl cc) {
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int32_t control = 0;
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switch (cc) {
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case StoreCacheControl::L1UC_L2UC_L3UC:
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case StoreCacheControl::L1UC_L2UC_L3WB:
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case StoreCacheControl::L1UC_L2WB_L3UC:
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case StoreCacheControl::L1UC_L2WB_L3WB:
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control = 1;
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break;
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case StoreCacheControl::L1WT_L2UC_L3UC:
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case StoreCacheControl::L1WT_L2UC_L3WB:
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case StoreCacheControl::L1WT_L2WB_L3UC:
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case StoreCacheControl::L1WT_L2WB_L3WB:
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control = 2;
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break;
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case StoreCacheControl::L1S_L2UC_L3UC:
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case StoreCacheControl::L1S_L2UC_L3WB:
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case StoreCacheControl::L1S_L2WB_L3UC:
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case StoreCacheControl::L1S_L2WB_L3WB:
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control = 3;
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break;
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case StoreCacheControl::L1WB_L2UC_L3UC:
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case StoreCacheControl::L1WB_L2WB_L3UC:
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case StoreCacheControl::L1WB_L2UC_L3WB:
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control = 4;
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break;
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}
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return control;
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}
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static int32_t getL3CacheControl(LoadCacheControl cc) {
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int32_t control = 0;
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switch (cc) {
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case LoadCacheControl::L1UC_L2UC_L3UC:
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case LoadCacheControl::L1UC_L2C_L3UC:
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case LoadCacheControl::L1C_L2UC_L3UC:
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case LoadCacheControl::L1C_L2C_L3UC:
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case LoadCacheControl::L1S_L2UC_L3UC:
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case LoadCacheControl::L1S_L2C_L3UC:
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control = 1;
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break;
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case LoadCacheControl::L1UC_L2UC_L3C:
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case LoadCacheControl::L1UC_L2C_L3C:
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case LoadCacheControl::L1C_L2UC_L3C:
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case LoadCacheControl::L1C_L2C_L3C:
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case LoadCacheControl::L1S_L2UC_L3C:
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case LoadCacheControl::L1S_L2C_L3C:
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control = 2;
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break;
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case LoadCacheControl::INVALIDATE_READ:
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control = 4;
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break;
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}
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return control;
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}
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static int32_t getL3CacheControl(StoreCacheControl cc) {
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int32_t control = 0;
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switch (cc) {
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case StoreCacheControl::L1UC_L2UC_L3UC:
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case StoreCacheControl::L1UC_L2WB_L3UC:
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case StoreCacheControl::L1WT_L2UC_L3UC:
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case StoreCacheControl::L1WT_L2WB_L3UC:
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case StoreCacheControl::L1S_L2UC_L3UC:
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case StoreCacheControl::L1S_L2WB_L3UC:
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case StoreCacheControl::L1WB_L2UC_L3UC:
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case StoreCacheControl::L1WB_L2WB_L3UC:
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control = 1;
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break;
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case StoreCacheControl::L1UC_L2UC_L3WB:
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case StoreCacheControl::L1UC_L2WB_L3WB:
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case StoreCacheControl::L1WT_L2UC_L3WB:
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case StoreCacheControl::L1WT_L2WB_L3WB:
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case StoreCacheControl::L1S_L2UC_L3WB:
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case StoreCacheControl::L1S_L2WB_L3WB:
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case StoreCacheControl::L1WB_L2UC_L3WB:
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control = 2;
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break;
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}
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return control;
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}
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static std::optional<LoadCacheControl> getCacheControl(PrefetchOp op) {
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return op.getCacheControl();
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}
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static std::optional<LoadCacheControl> getCacheControl(BlockLoad2dOp op) {
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return op.getCacheControl();
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}
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static std::optional<LoadCacheControl> getCacheControl(BlockLoadOp op) {
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return op.getCacheControl();
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}
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static std::optional<LoadCacheControl> getCacheControl(BlockPrefetch2dOp op) {
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return op.getCacheControl();
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}
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static std::optional<StoreCacheControl> getCacheControl(BlockStore2dOp op) {
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return op.getCacheControl();
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}
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static std::optional<StoreCacheControl> getCacheControl(BlockStoreOp op) {
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return op.getCacheControl();
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}
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static std::optional<LoadCacheControl> getCacheControl(LLVM::LoadOp op) {
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if (op->hasAttr("cache_control")) {
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auto attr = op->getAttrOfType<xevm::LoadCacheControlAttr>("cache_control");
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if (!attr)
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return std::nullopt;
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return std::optional<LoadCacheControl>(attr.getValue());
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}
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return std::nullopt;
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}
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static std::optional<StoreCacheControl> getCacheControl(LLVM::StoreOp op) {
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if (op->hasAttr("cache_control")) {
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auto attr = op->getAttrOfType<xevm::StoreCacheControlAttr>("cache_control");
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if (!attr)
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return std::nullopt;
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return std::optional<StoreCacheControl>(attr.getValue());
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}
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return std::nullopt;
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}
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template <typename OpType>
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int32_t getL1CacheControl(OpType op) {
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return getL1CacheControl(*getCacheControl(op));
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}
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template <typename OpType>
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int32_t getL3CacheControl(OpType op) {
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return getL3CacheControl(*getCacheControl(op));
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}
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template <typename OpType>
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static std::optional<ArrayAttr>
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getCacheControlMetadata(ConversionPatternRewriter &rewriter, OpType op) {
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if (!getCacheControl(op))
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return {};
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constexpr int32_t decorationCacheControlArity{4};
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constexpr int32_t loadCacheControlKey{6442};
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constexpr int32_t storeCacheControlKey{6443};
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constexpr bool isLoad = std::is_same_v<OpType, BlockLoad2dOp> ||
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std::is_same_v<OpType, BlockPrefetch2dOp> ||
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std::is_same_v<OpType, LLVM::LoadOp> ||
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std::is_same_v<OpType, BlockLoadOp> ||
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std::is_same_v<OpType, PrefetchOp>;
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const int32_t controlKey{isLoad ? loadCacheControlKey : storeCacheControlKey};
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SmallVector<int32_t, decorationCacheControlArity> decorationsL1{
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controlKey, 0, getL1CacheControl<OpType>(op), 0};
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SmallVector<int32_t, decorationCacheControlArity> decorationsL3{
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controlKey, 1, getL3CacheControl<OpType>(op), 0};
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auto arrayAttrL1 = rewriter.getI32ArrayAttr(decorationsL1);
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auto arrayAttrL3 = rewriter.getI32ArrayAttr(decorationsL3);
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SmallVector<Attribute, 2> combinedAttrs = {arrayAttrL1, arrayAttrL3};
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return rewriter.getArrayAttr(combinedAttrs);
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}
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static LLVM::CallOp createDeviceFunctionCall(
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ConversionPatternRewriter &rewriter, StringRef funcName, Type retType,
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ArrayRef<Type> argTypes, ArrayRef<Value> args,
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mlir::ArrayRef<std::pair<unsigned, mlir::StringRef>> paramAttrs,
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LLVMFuncAttributeOptions funcAttributeOptions, Operation *op) {
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auto *moduleOp = op->getParentWithTrait<OpTrait::SymbolTable>();
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assert(moduleOp && "Expecting module");
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Location loc = op->getLoc();
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auto funcOpRes =
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LLVM::lookupOrCreateFn(rewriter, moduleOp, funcName, argTypes, retType);
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assert(!failed(funcOpRes));
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LLVM::LLVMFuncOp funcOp = funcOpRes.value();
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funcOp.setCConv(LLVM::cconv::CConv::SPIR_FUNC);
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funcOp.setConvergent(funcAttributeOptions.isConvergent);
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funcOp.setNoUnwind(funcAttributeOptions.isNoUnwind);
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funcOp.setWillReturn(funcAttributeOptions.isWillReturn);
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if (funcAttributeOptions.memEffectsAttr)
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funcOp.setMemoryEffectsAttr(funcAttributeOptions.memEffectsAttr);
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for (auto [idx, attrName] : paramAttrs)
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funcOp.setArgAttr(idx, attrName, rewriter.getUnitAttr());
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auto callOp = LLVM::CallOp::create(rewriter, loc, funcOp, args);
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callOp->setAttrs(funcOp->getAttrs());
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return callOp;
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}
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class MMAToOCLPattern : public OpConversionPattern<xevm::MMAOp> {
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using OpConversionPattern::OpConversionPattern;
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LogicalResult
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matchAndRewrite(xevm::MMAOp op, xevm::MMAOp::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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if (!op.getC()) {
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return rewriter.notifyMatchFailure(op, "OCL requires C operand");
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}
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auto precisionA = op.getTypes().getA();
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auto precisionB = op.getTypes().getB();
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auto precisionC = op.getTypes().getC();
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auto precisionD = op.getTypes().getD();
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if (precisionC != precisionD) {
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return rewriter.notifyMatchFailure(op, "type of C and D need to match");
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}
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if (precisionC != xevm::ElemType::S32 &&
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precisionC != xevm::ElemType::F32 &&
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precisionC != xevm::ElemType::F16 &&
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precisionC != xevm::ElemType::BF16) {
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return rewriter.notifyMatchFailure(
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op, "type of C and D must be S32, F32, F16 or BF16");
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}
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if (precisionA == xevm::ElemType::S32 ||
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precisionA == xevm::ElemType::F32) {
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return rewriter.notifyMatchFailure(op, "type of A cannot be S32 or F32");
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}
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if (precisionB == xevm::ElemType::S32 ||
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precisionB == xevm::ElemType::F32) {
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return rewriter.notifyMatchFailure(op, "type of B cannot be S32 or F32");
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}
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constexpr uint32_t bitWidthPackedA{16};
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constexpr uint32_t bitWidthPackedB{32};
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auto loc = op.getLoc();
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auto castIfNeeded = [&](Value val, Type packedType) -> Value {
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VectorType origTy = cast<VectorType>(val.getType());
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const uint32_t vecBitSize =
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origTy.getNumElements() *
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origTy.getElementType().getIntOrFloatBitWidth();
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VectorType newTy = VectorType::get(
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vecBitSize / packedType.getIntOrFloatBitWidth(), packedType);
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if (origTy != newTy)
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val = LLVM::BitcastOp::create(rewriter, loc, newTy, val);
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return val;
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};
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Value a = op.getA();
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Type packedAType = (op.getTypes().getA() == xevm::ElemType::TF32)
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? cast<Type>(rewriter.getF32Type())
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: rewriter.getIntegerType(bitWidthPackedA);
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a = castIfNeeded(a, packedAType);
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Value b = op.getB();
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Type packedBType = (op.getTypes().getB() == xevm::ElemType::TF32)
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? cast<Type>(rewriter.getF32Type())
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: rewriter.getIntegerType(bitWidthPackedB);
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b = castIfNeeded(b, packedBType);
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Value c = op.getC();
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VectorType cOrigTy = cast<VectorType>(c.getType());
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VectorType resOrigTy = cast<VectorType>(op->getResultTypes()[0]);
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assert(cOrigTy == resOrigTy && "Accumulator and result type mismatch");
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// OCL builtins encode bfloat16 as int16
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VectorType cTy =
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cOrigTy.getElementType().isBF16()
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? VectorType::get(cOrigTy.getShape(), rewriter.getIntegerType(16))
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: cOrigTy;
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VectorType resTy = cTy;
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if (cOrigTy != cTy)
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c = LLVM::BitcastOp::create(rewriter, loc, cTy, c);
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constexpr int32_t systolicDepth{8};
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std::string fnName =
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llvm::formatv("intel_sub_group_{0}_{1}_matrix_mad_k{2}",
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stringifyElemType(op.getTypes().getA()).str(),
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stringifyElemType(op.getTypes().getB()).str(),
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systolicDepth *
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getNumOperandsPerDword(op.getTypes().getA()))
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.str();
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SmallVector<Type> argTypes{a.getType(), b.getType(), cTy};
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fnName = mangle(fnName, argTypes);
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SmallVector<Value> args{a, b, c};
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auto memAttr = rewriter.getAttr<LLVM::MemoryEffectsAttr>(
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/*other=*/LLVM::ModRefInfo::NoModRef,
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/*argMem=*/LLVM::ModRefInfo::NoModRef,
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/*inaccessibleMem=*/LLVM::ModRefInfo::NoModRef,
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/*errnoMem=*/LLVM::ModRefInfo::NoModRef,
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/*targetMem0=*/LLVM::ModRefInfo::NoModRef,
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/*targetMem1=*/LLVM::ModRefInfo::NoModRef);
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auto funcAttrs = convergentNoUnwindWillReturnAttrs;
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funcAttrs.memEffectsAttr = memAttr;
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Value result =
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createDeviceFunctionCall(rewriter, fnName, resTy, argTypes, args, {},
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funcAttrs, op.getOperation())
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->getResult(0);
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if (resOrigTy != resTy)
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result = LLVM::BitcastOp::create(rewriter, loc, resOrigTy, result);
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rewriter.replaceOp(op, result);
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return success();
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}
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private:
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static unsigned getNumOperandsPerDword(xevm::ElemType pTy) {
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switch (pTy) {
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case xevm::ElemType::TF32:
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return 1;
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case xevm::ElemType::BF16:
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case xevm::ElemType::F16:
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return 2;
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case xevm::ElemType::U8:
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case xevm::ElemType::S8:
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return 4;
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default:
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llvm_unreachable("unsupported xevm::ElemType");
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}
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}
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};
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class PrefetchToOCLPattern : public OpConversionPattern<PrefetchOp> {
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using OpConversionPattern::OpConversionPattern;
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LogicalResult
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matchAndRewrite(PrefetchOp op, PrefetchOp::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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auto loc = op.getLoc();
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const std::string fnName{"_Z8prefetchPU3AS1Kcm"};
|
|
Value one =
|
|
LLVM::ConstantOp::create(rewriter, loc, rewriter.getI64Type(), 1);
|
|
SmallVector<Value> args{op.getPtr(), one};
|
|
SmallVector<Type> argTypes;
|
|
for (auto arg : args)
|
|
argTypes.push_back(arg.getType());
|
|
auto funcAttr = noUnwindAttrs;
|
|
auto memAttr = rewriter.getAttr<LLVM::MemoryEffectsAttr>(
|
|
/*other=*/LLVM::ModRefInfo::NoModRef,
|
|
/*argMem=*/LLVM::ModRefInfo::Ref,
|
|
/*inaccessibleMem=*/LLVM::ModRefInfo::NoModRef,
|
|
/*errnoMem=*/LLVM::ModRefInfo::NoModRef,
|
|
/*targetMem0=*/LLVM::ModRefInfo::NoModRef,
|
|
/*targetMem1=*/LLVM::ModRefInfo::NoModRef);
|
|
funcAttr.memEffectsAttr = memAttr;
|
|
|
|
LLVM::CallOp call = createDeviceFunctionCall(
|
|
rewriter, fnName, LLVM::LLVMVoidType::get(rewriter.getContext()),
|
|
argTypes, args, {}, funcAttr, op.getOperation());
|
|
if (std::optional<ArrayAttr> optCacheControls =
|
|
getCacheControlMetadata(rewriter, op))
|
|
call->setAttr(XeVMDialect::getCacheControlsAttrName(), *optCacheControls);
|
|
rewriter.eraseOp(op);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
class MemfenceToOCLPattern : public OpConversionPattern<MemfenceOp> {
|
|
using OpConversionPattern::OpConversionPattern;
|
|
LogicalResult
|
|
matchAndRewrite(MemfenceOp op, MemfenceOp::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
auto loc = op.getLoc();
|
|
const std::string fnName{"atomic_work_item_fence"};
|
|
int memScope, addrSpace;
|
|
switch (op.getAddrspace()) {
|
|
case xevm::AddrSpace::SHARED:
|
|
addrSpace = 1; // CLK_LOCAL_MEM_FENCE
|
|
break;
|
|
case xevm::AddrSpace::GLOBAL:
|
|
addrSpace = 2; // CLK_GLOBAL_MEM_FENCE
|
|
break;
|
|
default:
|
|
// GENERIC is not supported in OpenCL
|
|
return rewriter.notifyMatchFailure(
|
|
op, "Fence only supports global and shared address spaces.");
|
|
}
|
|
switch (op.getScope()) {
|
|
case xevm::MemScope::WORKGROUP:
|
|
memScope = 1;
|
|
break;
|
|
case xevm::MemScope::DEVICE:
|
|
memScope = 2;
|
|
break;
|
|
default:
|
|
// CLUSTER and SYSTEM are not supported in OpenCL
|
|
return rewriter.notifyMatchFailure(
|
|
op, "Fence only supports workgroup and device memory scopes.");
|
|
}
|
|
Type i32Type = rewriter.getI32Type();
|
|
Value acqRel = LLVM::ConstantOp::create(rewriter, loc, i32Type, 4);
|
|
Value memScopeConst =
|
|
LLVM::ConstantOp::create(rewriter, loc, i32Type, memScope);
|
|
Value addrSpaceConst =
|
|
LLVM::ConstantOp::create(rewriter, loc, i32Type, addrSpace);
|
|
SmallVector<Value> args{addrSpaceConst, acqRel, memScopeConst};
|
|
SmallVector<Type> argTypes{3, i32Type};
|
|
createDeviceFunctionCall(rewriter, mangle(fnName, argTypes),
|
|
LLVM::LLVMVoidType::get(rewriter.getContext()),
|
|
argTypes, args, {}, noUnwindAttrs,
|
|
op.getOperation());
|
|
rewriter.eraseOp(op);
|
|
return success();
|
|
}
|
|
};
|
|
template <typename OpType>
|
|
class LoadStorePrefetchToOCLPattern : public OpConversionPattern<OpType> {
|
|
using OpConversionPattern<OpType>::OpConversionPattern;
|
|
LogicalResult
|
|
matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
constexpr bool isLoad = std::is_same_v<OpType, BlockLoad2dOp>;
|
|
constexpr bool isPrefetch = std::is_same_v<OpType, BlockPrefetch2dOp>;
|
|
|
|
auto loc = op.getLoc();
|
|
VectorType vecType;
|
|
bool packReg = false;
|
|
bool transpose = false;
|
|
if constexpr (isLoad) {
|
|
vecType = op.getRes().getType();
|
|
packReg = op.getPackRegister();
|
|
transpose = op.getTranspose();
|
|
} else if constexpr (!isPrefetch) {
|
|
vecType = op.getStoredVal().getType();
|
|
}
|
|
|
|
auto i32Type = rewriter.getI32Type();
|
|
Value byteCoord =
|
|
LLVM::UndefOp::create(rewriter, loc, VectorType::get(2, i32Type));
|
|
Value zero = LLVM::ConstantOp::create(rewriter, loc, i32Type, 0);
|
|
Value one = LLVM::ConstantOp::create(rewriter, loc, i32Type, 1);
|
|
byteCoord = LLVM::InsertElementOp::create(
|
|
rewriter, loc, VectorType::get(2, i32Type), byteCoord, op.getX(), zero);
|
|
byteCoord = LLVM::InsertElementOp::create(
|
|
rewriter, loc, VectorType::get(2, i32Type), byteCoord, op.getY(), one);
|
|
SmallVector<Value> args{op.getPtr(), op.getBaseWidth(), op.getBaseHeight(),
|
|
op.getBasePitch(), byteCoord};
|
|
SmallVector<Type> retTypes;
|
|
Value spvLoadDstPtr;
|
|
std::string funcName{"intel_sub_group_2d_block_"};
|
|
std::string bitWidthId;
|
|
LLVMFuncAttributeOptions funcAttr{noUnwindWillReturnAttrs};
|
|
SmallVector<std::pair<unsigned, StringRef>, 4> paramAttrs;
|
|
if constexpr (isPrefetch) { // Prefetch
|
|
funcName += "prefetch";
|
|
paramAttrs = {std::make_pair(0, LLVM::LLVMDialect::getNonNullAttrName())};
|
|
auto memAttr = rewriter.getAttr<LLVM::MemoryEffectsAttr>(
|
|
/*other=*/LLVM::ModRefInfo::NoModRef,
|
|
/*argMem=*/LLVM::ModRefInfo::Ref,
|
|
/*inaccessibleMem=*/LLVM::ModRefInfo::NoModRef,
|
|
/*errnoMem=*/LLVM::ModRefInfo::NoModRef,
|
|
/*targetMem0=*/LLVM::ModRefInfo::NoModRef,
|
|
/*targetMem1=*/LLVM::ModRefInfo::NoModRef);
|
|
funcAttr = noUnwindAttrs;
|
|
funcAttr.memEffectsAttr = memAttr;
|
|
} else {
|
|
auto vecElemType = vecType.getElementType();
|
|
auto vecElemBitWidth = vecElemType.getIntOrFloatBitWidth();
|
|
Value numElems = LLVM::ConstantOp::create(rewriter, loc, i32Type,
|
|
vecType.getNumElements());
|
|
auto dstOrSrcPtr = LLVM::AllocaOp::create(
|
|
rewriter, loc, LLVM::LLVMPointerType::get(rewriter.getContext()),
|
|
vecElemType, numElems);
|
|
args.push_back(dstOrSrcPtr);
|
|
if constexpr (isLoad) { // Load
|
|
funcName += "read";
|
|
bitWidthId = getTypeMangling(vecElemType, /*isUnsigned=*/true);
|
|
if (packReg)
|
|
funcName += "_transform";
|
|
else if (transpose)
|
|
funcName += "_transpose";
|
|
spvLoadDstPtr = dstOrSrcPtr;
|
|
retTypes.push_back(vecType);
|
|
paramAttrs = {
|
|
std::make_pair(0, LLVM::LLVMDialect::getNonNullAttrName()),
|
|
std::make_pair(0, LLVM::LLVMDialect::getReadonlyAttrName()),
|
|
std::make_pair(5, LLVM::LLVMDialect::getNonNullAttrName()),
|
|
std::make_pair(5, LLVM::LLVMDialect::getWriteOnlyAttrName()),
|
|
};
|
|
} else { // Store
|
|
funcName += "write";
|
|
bitWidthId = (vecElemBitWidth == 32)
|
|
? "j"
|
|
: ((vecElemBitWidth == 16) ? "t" : "h");
|
|
LLVM::StoreOp::create(rewriter, loc, op.getStoredVal(), dstOrSrcPtr);
|
|
paramAttrs = {
|
|
std::make_pair(0, LLVM::LLVMDialect::getNonNullAttrName()),
|
|
std::make_pair(0, LLVM::LLVMDialect::getWriteOnlyAttrName()),
|
|
std::make_pair(5, LLVM::LLVMDialect::getNonNullAttrName()),
|
|
std::make_pair(5, LLVM::LLVMDialect::getReadonlyAttrName()),
|
|
};
|
|
}
|
|
}
|
|
|
|
funcName =
|
|
llvm::formatv("{0}_{1}b_{2}r{3}x{4}c", funcName, op.getElemSizeInBits(),
|
|
op.getTileHeight(), op.getTileWidth(), op.getVBlocks())
|
|
.str();
|
|
std::string prefetchCode("");
|
|
if (!isPrefetch)
|
|
prefetchCode += "P";
|
|
funcName = llvm::formatv("_Z{0}{1}PU3AS1viiiDv2_i{2}{3}", funcName.size(),
|
|
funcName, prefetchCode, bitWidthId)
|
|
.str();
|
|
SmallVector<Type> argTypes;
|
|
for (auto arg : args) {
|
|
argTypes.push_back(arg.getType());
|
|
}
|
|
LLVM::CallOp call = createDeviceFunctionCall(
|
|
rewriter, funcName, LLVM::LLVMVoidType::get(rewriter.getContext()),
|
|
argTypes, args, paramAttrs, funcAttr, op.getOperation());
|
|
if (std::optional<ArrayAttr> optCacheControls =
|
|
getCacheControlMetadata(rewriter, op)) {
|
|
call->setAttr(XeVMDialect::getCacheControlsAttrName(), *optCacheControls);
|
|
}
|
|
if constexpr (isLoad)
|
|
rewriter.replaceOp(
|
|
op, LLVM::LoadOp::create(rewriter, loc, vecType, spvLoadDstPtr));
|
|
else
|
|
rewriter.eraseOp(op);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
template <typename OpType>
|
|
class BlockLoadStore1DToOCLPattern : public OpConversionPattern<OpType> {
|
|
using OpConversionPattern<OpType>::OpConversionPattern;
|
|
LogicalResult
|
|
matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
constexpr bool isStore = std::is_same_v<OpType, xevm::BlockStoreOp>;
|
|
// Get OpenCL function name
|
|
// https://registry.khronos.org/OpenCL/extensions/
|
|
// intel/cl_intel_subgroup_local_block_io.html
|
|
std::string funcName{"intel_sub_group_block_"};
|
|
// Value or Result type can be vector or scalar
|
|
Type valOrResTy;
|
|
if constexpr (isStore) {
|
|
funcName += "write_u";
|
|
valOrResTy = op.getVal().getType();
|
|
} else {
|
|
funcName += "read_u";
|
|
valOrResTy = op.getType();
|
|
}
|
|
// Get element type of the vector/scalar
|
|
VectorType vecTy = dyn_cast<VectorType>(valOrResTy);
|
|
Type elemType = vecTy ? vecTy.getElementType() : valOrResTy;
|
|
funcName += getTypeMangling(elemType);
|
|
if (vecTy)
|
|
funcName += std::to_string(vecTy.getNumElements());
|
|
SmallVector<Type, 2> argTypes{};
|
|
// XeVM BlockLoad/StoreOp always use signless integer types
|
|
// but OpenCL builtins expect unsigned types
|
|
// use unsigned types for mangling
|
|
SmallVector<bool, 2> isUnsigned{};
|
|
// arg0: pointer to the src/dst address
|
|
// arg1 - only if store : vector to store
|
|
// Prepare arguments
|
|
SmallVector<Value, 2> args{};
|
|
args.push_back(op.getPtr());
|
|
argTypes.push_back(op.getPtr().getType());
|
|
isUnsigned.push_back(true);
|
|
Type retType;
|
|
if constexpr (isStore) {
|
|
args.push_back(op.getVal());
|
|
argTypes.push_back(op.getVal().getType());
|
|
isUnsigned.push_back(true);
|
|
retType = LLVM::LLVMVoidType::get(rewriter.getContext());
|
|
} else {
|
|
retType = valOrResTy;
|
|
}
|
|
funcName = std::string("_Z") + std::to_string(funcName.size()) + funcName +
|
|
"PU3AS" +
|
|
std::to_string(op.getPtr().getType().getAddressSpace());
|
|
funcName += getTypeMangling(elemType, /*isUnsigned=*/true);
|
|
if constexpr (isStore)
|
|
funcName += getTypeMangling(valOrResTy, /*isUnsigned=*/true);
|
|
LLVMFuncAttributeOptions funcAttr{noUnwindWillReturnAttrs};
|
|
|
|
LLVM::CallOp call =
|
|
createDeviceFunctionCall(rewriter, funcName, retType, argTypes, args,
|
|
{}, funcAttr, op.getOperation());
|
|
if (std::optional<ArrayAttr> optCacheControls =
|
|
getCacheControlMetadata(rewriter, op)) {
|
|
call->setAttr(XeVMDialect::getCacheControlsAttrName(), *optCacheControls);
|
|
}
|
|
if constexpr (isStore)
|
|
rewriter.eraseOp(op);
|
|
else
|
|
rewriter.replaceOp(op, call->getResult(0));
|
|
return success();
|
|
}
|
|
};
|
|
|
|
template <typename OpType>
|
|
class LLVMLoadStoreToOCLPattern : public OpConversionPattern<OpType> {
|
|
using OpConversionPattern<OpType>::OpConversionPattern;
|
|
LogicalResult
|
|
matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
if (!op->hasAttr("cache_control"))
|
|
return failure();
|
|
std::optional<ArrayAttr> optCacheControls =
|
|
getCacheControlMetadata(rewriter, op);
|
|
op->setAttr(XeVMDialect::getCacheControlsAttrName(), *optCacheControls);
|
|
op->removeAttr("cache_control");
|
|
return success();
|
|
}
|
|
};
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// GPU index id operations
|
|
//===----------------------------------------------------------------------===//
|
|
/*
|
|
// Launch Config ops
|
|
// dimidx - x, y, z - is fixed to i32
|
|
// return type is set by XeVM type converter
|
|
// get_local_id
|
|
xevm::WorkitemIdXOp;
|
|
xevm::WorkitemIdYOp;
|
|
xevm::WorkitemIdZOp;
|
|
// get_local_size
|
|
xevm::WorkgroupDimXOp;
|
|
xevm::WorkgroupDimYOp;
|
|
xevm::WorkgroupDimZOp;
|
|
// get_group_id
|
|
xevm::WorkgroupIdXOp;
|
|
xevm::WorkgroupIdYOp;
|
|
xevm::WorkgroupIdZOp;
|
|
// get_num_groups
|
|
xevm::GridDimXOp;
|
|
xevm::GridDimYOp;
|
|
xevm::GridDimZOp;
|
|
// get_global_id : to be added if needed
|
|
*/
|
|
|
|
// Helpers to get the OpenCL function name and dimension argument for each op.
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkitemIdXOp) {
|
|
return {"get_local_id", 0};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkitemIdYOp) {
|
|
return {"get_local_id", 1};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkitemIdZOp) {
|
|
return {"get_local_id", 2};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkgroupDimXOp) {
|
|
return {"get_local_size", 0};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkgroupDimYOp) {
|
|
return {"get_local_size", 1};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkgroupDimZOp) {
|
|
return {"get_local_size", 2};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkgroupIdXOp) {
|
|
return {"get_group_id", 0};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkgroupIdYOp) {
|
|
return {"get_group_id", 1};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::WorkgroupIdZOp) {
|
|
return {"get_group_id", 2};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::GridDimXOp) {
|
|
return {"get_num_groups", 0};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::GridDimYOp) {
|
|
return {"get_num_groups", 1};
|
|
}
|
|
static std::pair<StringRef, int64_t> getConfig(xevm::GridDimZOp) {
|
|
return {"get_num_groups", 2};
|
|
}
|
|
/// Replace `xevm.*` with an `llvm.call` to the corresponding OpenCL func with
|
|
/// a constant argument for the dimension - x, y or z.
|
|
template <typename OpType>
|
|
class LaunchConfigOpToOCLPattern : public OpConversionPattern<OpType> {
|
|
using OpConversionPattern<OpType>::OpConversionPattern;
|
|
LogicalResult
|
|
matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Location loc = op->getLoc();
|
|
auto [baseName, dim] = getConfig(op);
|
|
Type dimTy = rewriter.getI32Type();
|
|
Value dimVal = LLVM::ConstantOp::create(rewriter, loc, dimTy,
|
|
static_cast<int64_t>(dim));
|
|
std::string func = mangle(baseName, {dimTy}, {true});
|
|
Type resTy = op.getType();
|
|
auto call =
|
|
createDeviceFunctionCall(rewriter, func, resTy, {dimTy}, {dimVal}, {},
|
|
noUnwindWillReturnAttrs, op.getOperation());
|
|
constexpr auto noModRef = LLVM::ModRefInfo::NoModRef;
|
|
auto memAttr = rewriter.getAttr<LLVM::MemoryEffectsAttr>(
|
|
/*other=*/noModRef,
|
|
/*argMem=*/noModRef, /*inaccessibleMem=*/noModRef,
|
|
/*errnoMem=*/noModRef,
|
|
/*targetMem0=*/noModRef,
|
|
/*targetMem1=*/noModRef);
|
|
call.setMemoryEffectsAttr(memAttr);
|
|
rewriter.replaceOp(op, call);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
/*
|
|
// Subgroup ops
|
|
// get_sub_group_local_id
|
|
xevm::LaneIdOp;
|
|
// get_sub_group_id
|
|
xevm::SubgroupIdOp;
|
|
// get_sub_group_size
|
|
xevm::SubgroupSizeOp;
|
|
// get_num_sub_groups : to be added if needed
|
|
*/
|
|
|
|
// Helpers to get the OpenCL function name for each op.
|
|
static StringRef getConfig(xevm::LaneIdOp) { return "get_sub_group_local_id"; }
|
|
static StringRef getConfig(xevm::SubgroupIdOp) { return "get_sub_group_id"; }
|
|
static StringRef getConfig(xevm::SubgroupSizeOp) {
|
|
return "get_sub_group_size";
|
|
}
|
|
template <typename OpType>
|
|
class SubgroupOpWorkitemOpToOCLPattern : public OpConversionPattern<OpType> {
|
|
using OpConversionPattern<OpType>::OpConversionPattern;
|
|
LogicalResult
|
|
matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
std::string func = mangle(getConfig(op).str(), {});
|
|
Type resTy = op.getType();
|
|
auto call =
|
|
createDeviceFunctionCall(rewriter, func, resTy, {}, {}, {},
|
|
noUnwindWillReturnAttrs, op.getOperation());
|
|
constexpr auto noModRef = LLVM::ModRefInfo::NoModRef;
|
|
auto memAttr = rewriter.getAttr<LLVM::MemoryEffectsAttr>(
|
|
/*other=*/noModRef,
|
|
/*argMem=*/noModRef, /*inaccessibleMem=*/noModRef,
|
|
/*errnoMem=*/noModRef,
|
|
/*targetMem0=*/noModRef,
|
|
/*targetMem1=*/noModRef);
|
|
call.setMemoryEffectsAttr(memAttr);
|
|
rewriter.replaceOp(op, call);
|
|
return success();
|
|
}
|
|
};
|
|
|
|
static bool isExtractingContiguousSlice(LLVM::ShuffleVectorOp op) {
|
|
if (op.getV1() != op.getV2())
|
|
return false;
|
|
auto maskAttr = op.getMask();
|
|
int64_t firstIndex = maskAttr[0];
|
|
for (int64_t i = 1; i < static_cast<int64_t>(maskAttr.size()); ++i) {
|
|
int64_t index = maskAttr[i];
|
|
if (index != firstIndex + i)
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// Input vector of a shuffle vector op extracting a contiguous slice is an
|
|
// illegal vector in SPIRV kernel if the vector size is > 16 elements.
|
|
// To legalize this case, keep applying the following transformations until no
|
|
// more match:
|
|
// 1. keep hoisting the shuffle vector op past unary element-wise operations
|
|
// start with fpext, fptrunc and bitcast for now.
|
|
// 2. merge with another shuffle vector op
|
|
// 3. merge with load as a smaller load
|
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class HandleVectorExtractPattern
|
|
: public OpRewritePattern<LLVM::ShuffleVectorOp> {
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using OpRewritePattern<LLVM::ShuffleVectorOp>::OpRewritePattern;
|
|
|
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void initialize() { setHasBoundedRewriteRecursion(); }
|
|
|
|
LogicalResult matchAndRewrite(LLVM::ShuffleVectorOp op,
|
|
PatternRewriter &rewriter) const override {
|
|
|
|
if (!isExtractingContiguousSlice(op))
|
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return failure();
|
|
|
|
auto mask = op.getMask();
|
|
auto loc = op.getLoc();
|
|
auto ty = op.getType();
|
|
// Check source operand to determine rewrite pattern.
|
|
auto src = op.getV1();
|
|
// 1. Hoist past unary element-wise operations
|
|
if (auto srcOp = src.getDefiningOp()) {
|
|
if (isa<LLVM::FPExtOp>(srcOp) || isa<LLVM::FPTruncOp>(srcOp)) {
|
|
Value srcInput = srcOp->getOperand(0);
|
|
// Create new shuffle vector op with unary input as source.
|
|
auto srcVecTy = dyn_cast<VectorType>(srcInput.getType());
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|
auto newShuffleVecTy =
|
|
VectorType::get(mask.size(), srcVecTy.getElementType());
|
|
auto newShuffle = LLVM::ShuffleVectorOp::create(
|
|
rewriter, loc, newShuffleVecTy, srcInput, srcInput, mask);
|
|
// Create new unary op with new shuffle as input.
|
|
Value newUnaryOp;
|
|
if (isa<LLVM::FPExtOp>(srcOp)) {
|
|
newUnaryOp = LLVM::FPExtOp::create(rewriter, loc, ty, newShuffle);
|
|
} else {
|
|
newUnaryOp = LLVM::FPTruncOp::create(rewriter, loc, ty, newShuffle);
|
|
}
|
|
rewriter.replaceOp(op, newUnaryOp);
|
|
} else if (isa<LLVM::BitcastOp>(srcOp)) {
|
|
Value srcInput = srcOp->getOperand(0);
|
|
// Create new shuffle vector op with unary input as source.
|
|
auto srcInputVecTy = dyn_cast<VectorType>(srcInput.getType());
|
|
auto srcInputSize = srcInputVecTy.getNumElements();
|
|
auto srcResVecTy = dyn_cast<VectorType>(srcOp->getResult(0).getType());
|
|
auto srcResSize = srcResVecTy.getNumElements();
|
|
auto maskSize = static_cast<int32_t>(mask.size());
|
|
if (srcInputSize > srcResSize) {
|
|
return failure();
|
|
}
|
|
if (srcResSize % srcInputSize != 0) {
|
|
return failure();
|
|
}
|
|
auto maskScale = srcResSize / srcInputSize;
|
|
if (maskScale != 1) {
|
|
if (mask[0] % maskScale != 0) {
|
|
return failure();
|
|
}
|
|
// Create a new mask that maps to the source vector
|
|
SmallVector<int32_t> newMask;
|
|
int32_t newMaskSize = maskSize / maskScale;
|
|
int32_t maskStart = mask[0] / maskScale;
|
|
for (int32_t i = 0; i < newMaskSize; ++i) {
|
|
newMask.push_back(maskStart + i);
|
|
}
|
|
mask = newMask;
|
|
}
|
|
auto newShuffleVecTy =
|
|
VectorType::get(srcInputSize, srcInputVecTy.getElementType());
|
|
auto newShuffle = LLVM::ShuffleVectorOp::create(
|
|
rewriter, loc, newShuffleVecTy, srcInput, srcInput, mask);
|
|
// Create new unary op with new shuffle as input.
|
|
auto newBitcast =
|
|
LLVM::BitcastOp::create(rewriter, loc, ty, newShuffle);
|
|
rewriter.replaceOp(op, newBitcast);
|
|
} else if (isa<LLVM::ShuffleVectorOp>(srcOp)) {
|
|
// 2. Merge with another shuffle vector op
|
|
auto srcShuffle = cast<LLVM::ShuffleVectorOp>(srcOp);
|
|
auto srcMask = srcShuffle.getMask();
|
|
SmallVector<int32_t> combinedMask;
|
|
for (auto index : mask) {
|
|
combinedMask.push_back(srcMask[index]);
|
|
}
|
|
auto newShuffle = LLVM::ShuffleVectorOp::create(
|
|
rewriter, loc, ty, srcShuffle.getV1(), srcShuffle.getV1(),
|
|
DenseI32ArrayAttr::get(rewriter.getContext(), combinedMask));
|
|
rewriter.replaceOp(op, newShuffle);
|
|
} else if (isa<LLVM::LoadOp>(srcOp)) {
|
|
// 3. Merge with load as a smaller load
|
|
auto loadOp = cast<LLVM::LoadOp>(srcOp);
|
|
auto loadPtr = loadOp.getAddr();
|
|
auto loadTy = dyn_cast<VectorType>(loadOp.getType());
|
|
auto elemTy = loadTy.getElementType();
|
|
auto firstIndex = mask[0];
|
|
auto newVecTy = VectorType::get(mask.size(), elemTy);
|
|
// GEPOp is needed if first index is not zero
|
|
if (firstIndex) {
|
|
auto newPtr = LLVM::GEPOp::create(
|
|
rewriter, loc,
|
|
LLVM::LLVMPointerType::get(rewriter.getContext(),
|
|
loadPtr.getType().getAddressSpace()),
|
|
elemTy, loadPtr, ArrayRef<LLVM::GEPArg>{firstIndex});
|
|
auto newLoad = LLVM::LoadOp::create(rewriter, loc, newVecTy, newPtr);
|
|
rewriter.replaceOp(op, newLoad);
|
|
} else {
|
|
auto newLoad = LLVM::LoadOp::create(rewriter, loc, newVecTy, loadPtr);
|
|
rewriter.replaceOp(op, newLoad);
|
|
}
|
|
} else {
|
|
return failure();
|
|
}
|
|
}
|
|
return success();
|
|
}
|
|
};
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pass Definition
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
struct ConvertXeVMToLLVMPass
|
|
: public impl::ConvertXeVMToLLVMPassBase<ConvertXeVMToLLVMPass> {
|
|
using Base::Base;
|
|
|
|
void getDependentDialects(DialectRegistry ®istry) const override {
|
|
registry.insert<LLVM::LLVMDialect, XeVMDialect>();
|
|
}
|
|
|
|
void runOnOperation() override {
|
|
ConversionTarget target(getContext());
|
|
RewritePatternSet patterns(&getContext());
|
|
populateXeVMToLLVMConversionPatterns(target, patterns);
|
|
if (failed(applyPartialConversion(getOperation(), target,
|
|
std::move(patterns))))
|
|
signalPassFailure();
|
|
|
|
// Apply in-dialect lowerings to handle illegal vectors
|
|
{
|
|
RewritePatternSet vectorPatterns(&getContext());
|
|
vectorPatterns.add<HandleVectorExtractPattern>(&getContext());
|
|
GreedyRewriteConfig config{};
|
|
// folding can remove ops with temporary attributes used to
|
|
// represent LLVM metadata, so disable it here.
|
|
// Effectively just this single pattern is applied without any
|
|
// op folding patterns from dialects.
|
|
config.enableFolding(false);
|
|
// config.setMaxIterations(GreedyRewriteConfig::kNoLimit);
|
|
// config.setMaxNumRewrites(GreedyRewriteConfig::kNoLimit);
|
|
(void)applyPatternsGreedily(getOperation(), std::move(vectorPatterns),
|
|
config);
|
|
}
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pattern Population
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
void ::mlir::populateXeVMToLLVMConversionPatterns(ConversionTarget &target,
|
|
RewritePatternSet &patterns) {
|
|
target.addDynamicallyLegalDialect<LLVM::LLVMDialect>(
|
|
[](Operation *op) { return !op->hasAttr("cache_control"); });
|
|
target.addIllegalDialect<XeVMDialect>();
|
|
patterns.add<LoadStorePrefetchToOCLPattern<BlockLoad2dOp>,
|
|
LoadStorePrefetchToOCLPattern<BlockStore2dOp>,
|
|
LoadStorePrefetchToOCLPattern<BlockPrefetch2dOp>,
|
|
MMAToOCLPattern, MemfenceToOCLPattern, PrefetchToOCLPattern,
|
|
LLVMLoadStoreToOCLPattern<LLVM::LoadOp>,
|
|
LLVMLoadStoreToOCLPattern<LLVM::StoreOp>,
|
|
BlockLoadStore1DToOCLPattern<BlockLoadOp>,
|
|
BlockLoadStore1DToOCLPattern<BlockStoreOp>,
|
|
LaunchConfigOpToOCLPattern<WorkitemIdXOp>,
|
|
LaunchConfigOpToOCLPattern<WorkitemIdYOp>,
|
|
LaunchConfigOpToOCLPattern<WorkitemIdZOp>,
|
|
LaunchConfigOpToOCLPattern<WorkgroupDimXOp>,
|
|
LaunchConfigOpToOCLPattern<WorkgroupDimYOp>,
|
|
LaunchConfigOpToOCLPattern<WorkgroupDimZOp>,
|
|
LaunchConfigOpToOCLPattern<WorkgroupIdXOp>,
|
|
LaunchConfigOpToOCLPattern<WorkgroupIdYOp>,
|
|
LaunchConfigOpToOCLPattern<WorkgroupIdZOp>,
|
|
LaunchConfigOpToOCLPattern<GridDimXOp>,
|
|
LaunchConfigOpToOCLPattern<GridDimYOp>,
|
|
LaunchConfigOpToOCLPattern<GridDimZOp>,
|
|
SubgroupOpWorkitemOpToOCLPattern<LaneIdOp>,
|
|
SubgroupOpWorkitemOpToOCLPattern<SubgroupIdOp>,
|
|
SubgroupOpWorkitemOpToOCLPattern<SubgroupSizeOp>>(
|
|
patterns.getContext());
|
|
}
|