2ed3f49c49
The builder create methods are deprecated: https://mlir.llvm.org/deprecation/. See https://discourse.llvm.org/t/psa-opty-create-now-with-100-more-tab-complete/87339.
555 lines
18 KiB
C++
555 lines
18 KiB
C++
//===- BasicPtxBuilderInterface.td - PTX builder interface -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Defines the interface to build PTX (Parallel Thread Execution) from NVVM Ops
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// automatically. It is used by NVVM to LLVM pass.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/Diagnostics.h"
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#include "mlir/IR/Location.h"
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#include "mlir/IR/MLIRContext.h"
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#include "mlir/Support/LLVM.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/TypeSwitch.h"
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#include "llvm/Support/DebugLog.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "llvm/Support/LogicalResult.h"
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#include "llvm/Support/Regex.h"
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#define DEBUG_TYPE "ptx-builder"
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//===----------------------------------------------------------------------===//
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// BasicPtxBuilderInterface
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.cpp.inc"
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using namespace mlir;
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using namespace NVVM;
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static constexpr int64_t kSharedMemorySpace = 3;
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static FailureOr<char> getRegisterType(Type type, Location loc) {
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MLIRContext *ctx = type.getContext();
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auto i16 = IntegerType::get(ctx, 16);
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auto i32 = IntegerType::get(ctx, 32);
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auto f32 = Float32Type::get(ctx);
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auto getRegisterTypeForScalar = [&](Type type) -> FailureOr<char> {
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if (type.isInteger(1))
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return 'b';
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if (type.isInteger(16))
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return 'h';
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if (type.isInteger(32))
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return 'r';
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if (type.isInteger(64))
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return 'l';
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if (type.isF32())
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return 'f';
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if (type.isF64())
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return 'd';
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if (auto ptr = dyn_cast<LLVM::LLVMPointerType>(type)) {
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// Shared address spaces is addressed with 32-bit pointers.
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if (ptr.getAddressSpace() == kSharedMemorySpace) {
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return 'r';
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}
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return 'l';
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}
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// register type for struct is not supported.
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mlir::emitError(
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loc, "The register type could not be deduced from MLIR type. The ")
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<< type
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<< " is not supported. Supported types are:"
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"i1, i16, i32, i64, f32, f64,"
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"pointers.\nPlease use llvm.bitcast if you have different type. "
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"\nSee the constraints from here: "
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"https://docs.nvidia.com/cuda/inline-ptx-assembly/"
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"index.html#constraints";
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return failure();
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};
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// Packed registers
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if (auto v = dyn_cast<VectorType>(type)) {
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assert(v.getNumDynamicDims() == 0 && "Dynamic vectors are not supported");
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int64_t lanes = v.getNumElements();
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Type elem = v.getElementType();
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// Case 1. Single vector
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if (lanes <= 1)
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return getRegisterTypeForScalar(elem);
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// Case 2. Packed registers
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Type widened = elem;
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switch (lanes) {
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case 2:
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if (elem.isF16() || elem.isBF16()) // vector<2xf16>
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widened = f32;
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else if (elem.isFloat(8)) // vector<2xf8>
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widened = i16;
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break;
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case 4:
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if (elem.isInteger(8)) // vector<i8x4>
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widened = i32;
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else if (elem.isFloat(8)) // vector<f8x4>
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widened = f32;
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else if (elem.isFloat(4)) // vector<f4x4>
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widened = i16;
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break;
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// Other packing is not supported
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default:
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break;
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}
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return getRegisterTypeForScalar(widened);
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}
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return getRegisterTypeForScalar(type);
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}
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static FailureOr<char> getRegisterType(Value v, Location loc) {
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if (v.getDefiningOp<LLVM::ConstantOp>())
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return 'n';
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return getRegisterType(v.getType(), loc);
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}
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/// Extract every element of a struct value.
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static SmallVector<Value> extractStructElements(PatternRewriter &rewriter,
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Location loc, Value structVal) {
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auto structTy = dyn_cast<LLVM::LLVMStructType>(structVal.getType());
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assert(structTy && "expected LLVM struct");
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SmallVector<Value> elems;
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for (unsigned i : llvm::seq<unsigned>(0, structTy.getBody().size()))
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elems.push_back(LLVM::ExtractValueOp::create(rewriter, loc, structVal, i));
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return elems;
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}
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LogicalResult PtxBuilder::insertValue(Value v, PTXRegisterMod itype) {
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LDBG() << v << "\t Modifier : " << itype << "\n";
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registerModifiers.push_back(itype);
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Location loc = interfaceOp->getLoc();
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auto getModifier = [&]() -> const char * {
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switch (itype) {
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case PTXRegisterMod::Read:
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return "";
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case PTXRegisterMod::Write:
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return "=";
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case PTXRegisterMod::ReadWrite:
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// "Read-Write modifier is not actually supported
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// Interface will change it to "=" later and add integer mapping
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return "+";
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}
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llvm_unreachable("Unknown PTX register modifier");
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};
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auto addValue = [&](Value v) {
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if (itype == PTXRegisterMod::Read) {
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ptxOperands.push_back(v);
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return;
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}
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if (itype == PTXRegisterMod::ReadWrite)
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ptxOperands.push_back(v);
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hasResult = true;
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};
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llvm::raw_string_ostream ss(registerConstraints);
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// Handle Structs
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if (auto stype = dyn_cast<LLVM::LLVMStructType>(v.getType())) {
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if (itype == PTXRegisterMod::Write) {
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addValue(v);
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}
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for (auto [idx, t] : llvm::enumerate(stype.getBody())) {
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if (itype != PTXRegisterMod::Write) {
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Value extractValue =
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LLVM::ExtractValueOp::create(rewriter, loc, v, idx);
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addValue(extractValue);
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}
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if (itype == PTXRegisterMod::ReadWrite) {
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ss << idx << ",";
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} else {
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FailureOr<char> regType = getRegisterType(t, loc);
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if (failed(regType))
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return rewriter.notifyMatchFailure(loc,
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"failed to get register type");
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ss << getModifier() << regType.value() << ",";
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}
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}
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return success();
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}
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// Handle Scalars
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addValue(v);
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FailureOr<char> regType = getRegisterType(v, loc);
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if (failed(regType))
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return rewriter.notifyMatchFailure(loc, "failed to get register type");
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ss << getModifier() << regType.value() << ",";
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return success();
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}
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/// Check if the operation needs to pack and unpack results.
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static bool
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needsPackUnpack(BasicPtxBuilderInterface interfaceOp,
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bool needsManualRegisterMapping,
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SmallVectorImpl<PTXRegisterMod> ®isterModifiers) {
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if (needsManualRegisterMapping)
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return false;
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const unsigned writeOnlyVals = interfaceOp->getNumResults();
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const unsigned readWriteVals =
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llvm::count_if(registerModifiers, [](PTXRegisterMod m) {
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return m == PTXRegisterMod::ReadWrite;
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});
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return (writeOnlyVals + readWriteVals) > 1;
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}
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/// Pack the result types of the interface operation.
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/// If the operation has multiple results, it packs them into a struct
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/// type. Otherwise, it returns the original result types.
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static SmallVector<Type>
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packResultTypes(BasicPtxBuilderInterface interfaceOp,
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bool needsManualRegisterMapping,
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SmallVectorImpl<PTXRegisterMod> ®isterModifiers,
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SmallVectorImpl<Value> &ptxOperands) {
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MLIRContext *ctx = interfaceOp->getContext();
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TypeRange resultRange = interfaceOp->getResultTypes();
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if (!needsPackUnpack(interfaceOp, needsManualRegisterMapping,
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registerModifiers)) {
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// Single value path:
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if (interfaceOp->getResults().size() == 1)
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return SmallVector<Type>{resultRange.front()};
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// No declared results: if there is an RW, forward its type.
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for (auto [m, v] : llvm::zip(registerModifiers, ptxOperands))
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if (m == PTXRegisterMod::ReadWrite)
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return SmallVector<Type>{v.getType()};
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}
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SmallVector<Type> packed;
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for (auto [m, v] : llvm::zip(registerModifiers, ptxOperands))
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if (m == PTXRegisterMod::ReadWrite)
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packed.push_back(v.getType());
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for (Type t : resultRange)
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packed.push_back(t);
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if (packed.empty())
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return {};
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auto sTy = LLVM::LLVMStructType::getLiteral(ctx, packed, /*isPacked=*/false);
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return SmallVector<Type>{sTy};
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}
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/// Canonicalize the register constraints:
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/// - Turn every "+X" into "=X"
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/// - Append (at the very end) the 0-based indices of tokens that were "+X"
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/// Examples:
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/// "+f,+f,+r,=r,=r,r,r" -> "=f,=f,=r,=r,=r,r,r,0,1,2"
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/// "+f,+f,+r,=r,=r" -> "=f,=f,=r,=r,=r,0,1,2"
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static std::string canonicalizeRegisterConstraints(llvm::StringRef csv) {
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SmallVector<llvm::StringRef> toks;
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SmallVector<std::string> out;
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SmallVector<unsigned> plusIdx;
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csv.split(toks, ',');
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out.reserve(toks.size() + 8);
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for (unsigned i = 0, e = toks.size(); i < e; ++i) {
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StringRef t = toks[i].trim();
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if (t.consume_front("+")) {
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plusIdx.push_back(i);
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out.push_back(("=" + t).str());
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} else {
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out.push_back(t.str());
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}
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}
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// Append indices of original "+X" tokens.
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for (unsigned idx : plusIdx)
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out.push_back(std::to_string(idx));
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// Join back to CSV.
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std::string result;
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result.reserve(csv.size() + plusIdx.size() * 2);
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llvm::raw_string_ostream os(result);
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for (size_t i = 0; i < out.size(); ++i) {
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if (i)
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os << ',';
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os << out[i];
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}
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return os.str();
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}
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constexpr llvm::StringLiteral kReadWritePrefix{"rw"};
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constexpr llvm::StringLiteral kWriteOnlyPrefix{"w"};
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constexpr llvm::StringLiteral kReadOnlyPrefix{"r"};
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/// Returns a regex that matches {$rwN}, {$wN}, {$rN}
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static llvm::Regex getPredicateMappingRegex() {
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llvm::Regex rx(llvm::formatv(R"(\{\$({0}|{1}|{2})([0-9]+)\})",
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kReadWritePrefix, kWriteOnlyPrefix,
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kReadOnlyPrefix)
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.str());
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return rx;
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}
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void mlir::NVVM::countPlaceholderNumbers(
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StringRef ptxCode, llvm::SmallDenseSet<unsigned int> &seenRW,
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llvm::SmallDenseSet<unsigned int> &seenW,
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llvm::SmallDenseSet<unsigned int> &seenR,
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llvm::SmallVectorImpl<unsigned int> &rwNums,
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llvm::SmallVectorImpl<unsigned int> &wNums,
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llvm::SmallVectorImpl<unsigned int> &rNums) {
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llvm::Regex rx = getPredicateMappingRegex();
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StringRef rest = ptxCode;
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SmallVector<StringRef, 3> m; // 0: full, 1: kind, 2: number
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while (!rest.empty() && rx.match(rest, &m)) {
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unsigned num = 0;
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(void)m[2].getAsInteger(10, num);
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// Insert it into the vector only the first time we see this number
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if (m[1].equals_insensitive(kReadWritePrefix)) {
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if (seenRW.insert(num).second)
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rwNums.push_back(num);
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} else if (m[1].equals_insensitive(kWriteOnlyPrefix)) {
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if (seenW.insert(num).second)
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wNums.push_back(num);
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} else {
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if (seenR.insert(num).second)
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rNums.push_back(num);
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}
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const size_t advance = (size_t)(m[0].data() - rest.data()) + m[0].size();
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rest = rest.drop_front(advance);
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}
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}
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/// Rewrites `{$rwN}`, `{$wN}`, and `{$rN}` placeholders in `ptxCode` into
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/// compact `$K` indices:
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/// - All `rw*` first (sorted by N),
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/// - Then `w*`,
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/// - Then `r*`.
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/// If there a predicate, it comes always in the end.
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/// Each number is assigned once; duplicates are ignored.
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///
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/// Example Input:
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/// "{
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/// reg .pred p;
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/// setp.ge.s32 p, {$r0}, {$r1};"
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/// selp.s32 {$rw0}, {$r0}, {$r1}, p;
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/// selp.s32 {$rw1}, {$r0}, {$r1}, p;
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/// selp.s32 {$w0}, {$r0}, {$r1}, p;
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/// selp.s32 {$w1}, {$r0}, {$r1}, p;
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/// }\n"
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/// Example Output:
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/// "{
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/// reg .pred p;
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/// setp.ge.s32 p, $4, $5;"
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/// selp.s32 $0, $4, $5, p;
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/// selp.s32 $1, $4, $5, p;
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/// selp.s32 $2, $4, $5, p;
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/// selp.s32 $3, $4, $5, p;
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/// }\n"
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static std::string rewriteAsmPlaceholders(llvm::StringRef ptxCode) {
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llvm::SmallDenseSet<unsigned> seenRW, seenW, seenR;
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llvm::SmallVector<unsigned> rwNums, wNums, rNums;
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// Step 1. Count Register Placeholder numbers
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countPlaceholderNumbers(ptxCode, seenRW, seenW, seenR, rwNums, wNums, rNums);
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// Step 2. Sort the Register Placeholder numbers
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llvm::sort(rwNums);
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llvm::sort(wNums);
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llvm::sort(rNums);
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// Step 3. Create mapping from original to new IDs
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llvm::DenseMap<unsigned, unsigned> rwMap, wMap, rMap;
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unsigned nextId = 0;
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for (unsigned n : rwNums)
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rwMap[n] = nextId++;
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for (unsigned n : wNums)
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wMap[n] = nextId++;
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for (unsigned n : rNums)
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rMap[n] = nextId++;
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// Step 4. Rewrite the PTX code with new IDs
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std::string out;
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out.reserve(ptxCode.size());
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size_t prev = 0;
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StringRef rest = ptxCode;
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SmallVector<StringRef, 3> matches;
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llvm::Regex rx = getPredicateMappingRegex();
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while (!rest.empty() && rx.match(rest, &matches)) {
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// Compute absolute match bounds in the original buffer.
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size_t absStart = (size_t)(matches[0].data() - ptxCode.data());
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size_t absEnd = absStart + matches[0].size();
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// Emit text before the match.
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out.append(ptxCode.data() + prev, ptxCode.data() + absStart);
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// Emit compact $K
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unsigned num = 0;
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(void)matches[2].getAsInteger(10, num);
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unsigned id = 0;
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if (matches[1].equals_insensitive(kReadWritePrefix))
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id = rwMap.lookup(num);
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else if (matches[1].equals_insensitive(kWriteOnlyPrefix))
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id = wMap.lookup(num);
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else
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id = rMap.lookup(num);
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out.push_back('$');
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out += std::to_string(id);
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prev = absEnd;
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const size_t advance =
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(size_t)(matches[0].data() - rest.data()) + matches[0].size();
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rest = rest.drop_front(advance);
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}
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// Step 5. Tail.
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out.append(ptxCode.data() + prev, ptxCode.data() + ptxCode.size());
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return out;
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}
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LLVM::InlineAsmOp PtxBuilder::build() {
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auto asmDialectAttr = LLVM::AsmDialectAttr::get(interfaceOp->getContext(),
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LLVM::AsmDialect::AD_ATT);
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SmallVector<Type> resultTypes = packResultTypes(
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interfaceOp, needsManualRegisterMapping, registerModifiers, ptxOperands);
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// Remove the last comma from the constraints string.
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if (!registerConstraints.empty() &&
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registerConstraints[registerConstraints.size() - 1] == ',')
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registerConstraints.pop_back();
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registerConstraints = canonicalizeRegisterConstraints(registerConstraints);
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std::string ptxInstruction = interfaceOp.getPtx();
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if (!needsManualRegisterMapping)
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ptxInstruction = rewriteAsmPlaceholders(ptxInstruction);
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// Add the predicate to the asm string.
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if (interfaceOp.getPredicate().has_value() &&
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interfaceOp.getPredicate().value()) {
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std::string predicateStr = "@%";
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predicateStr += std::to_string((ptxOperands.size() - 1));
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ptxInstruction = predicateStr + " " + ptxInstruction;
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}
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// Tablegen doesn't accept $, so we use %, but inline assembly uses $.
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// Replace all % with $
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llvm::replace(ptxInstruction, '%', '$');
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return LLVM::InlineAsmOp::create(
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rewriter, interfaceOp->getLoc(),
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/*result types=*/resultTypes,
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/*operands=*/ptxOperands,
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/*asm_string=*/ptxInstruction,
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/*constraints=*/registerConstraints.data(),
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/*has_side_effects=*/interfaceOp.hasSideEffect(),
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/*is_align_stack=*/false, LLVM::TailCallKind::None,
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/*asm_dialect=*/asmDialectAttr,
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/*operand_attrs=*/ArrayAttr());
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}
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void PtxBuilder::buildAndReplaceOp() {
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LLVM::InlineAsmOp inlineAsmOp = build();
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LDBG() << "\n Generated PTX \n\t" << inlineAsmOp;
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// Case 0: no result at all → just erase wrapper op.
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if (!hasResult) {
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rewriter.eraseOp(interfaceOp);
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return;
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}
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if (needsManualRegisterMapping) {
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rewriter.replaceOp(interfaceOp, inlineAsmOp->getResults());
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return;
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}
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// Case 1: Simple path, return single scalar
|
|
if (!needsPackUnpack(interfaceOp, needsManualRegisterMapping,
|
|
registerModifiers)) {
|
|
if (inlineAsmOp->getNumResults() > 0) {
|
|
rewriter.replaceOp(interfaceOp, inlineAsmOp->getResults());
|
|
} else {
|
|
// RW-only case with no declared results: forward the RW value.
|
|
SmallVector<Value> results;
|
|
for (auto [m, v] : llvm::zip(registerModifiers, ptxOperands))
|
|
if (m == PTXRegisterMod::ReadWrite) {
|
|
results.push_back(v);
|
|
break;
|
|
}
|
|
rewriter.replaceOp(interfaceOp, results);
|
|
}
|
|
return;
|
|
}
|
|
|
|
const bool hasRW = llvm::any_of(registerModifiers, [](PTXRegisterMod m) {
|
|
return m == PTXRegisterMod::ReadWrite;
|
|
});
|
|
|
|
// All multi-value paths produce a single struct result we need to unpack.
|
|
assert(LLVM::LLVMStructType::classof(inlineAsmOp.getResultTypes().front()) &&
|
|
"expected struct return for multi-result inline asm");
|
|
Value structVal = inlineAsmOp.getResult(0);
|
|
SmallVector<Value> unpacked =
|
|
extractStructElements(rewriter, interfaceOp->getLoc(), structVal);
|
|
|
|
// Case 2: only declared results (no RW): replace the op with all unpacked.
|
|
if (!hasRW && interfaceOp->getResults().size() > 0) {
|
|
rewriter.replaceOp(interfaceOp, unpacked);
|
|
return;
|
|
}
|
|
|
|
// Case 3: RW-only (no declared results): update RW uses and erase wrapper.
|
|
if (hasRW && interfaceOp->getResults().size() == 0) {
|
|
unsigned idx = 0;
|
|
for (auto [m, v] : llvm::zip(registerModifiers, ptxOperands)) {
|
|
if (m != PTXRegisterMod::ReadWrite)
|
|
continue;
|
|
Value repl = unpacked[idx++];
|
|
v.replaceUsesWithIf(repl, [&](OpOperand &use) {
|
|
Operation *owner = use.getOwner();
|
|
return owner != interfaceOp && owner != inlineAsmOp;
|
|
});
|
|
}
|
|
rewriter.eraseOp(interfaceOp);
|
|
return;
|
|
}
|
|
|
|
// Case 4: mixed (RW + declared results).
|
|
{
|
|
// First rewrite RW operands in place.
|
|
unsigned idx = 0;
|
|
for (auto [m, v] : llvm::zip(registerModifiers, ptxOperands)) {
|
|
if (m != PTXRegisterMod::ReadWrite)
|
|
continue;
|
|
Value repl = unpacked[idx++];
|
|
v.replaceUsesWithIf(repl, [&](OpOperand &use) {
|
|
Operation *owner = use.getOwner();
|
|
return owner != interfaceOp && owner != inlineAsmOp;
|
|
});
|
|
}
|
|
// The remaining unpacked values correspond to the declared results.
|
|
SmallVector<Value> tail;
|
|
tail.reserve(unpacked.size() - idx);
|
|
for (unsigned i = idx, e = unpacked.size(); i < e; ++i)
|
|
tail.push_back(unpacked[i]);
|
|
|
|
rewriter.replaceOp(interfaceOp, tail);
|
|
}
|
|
}
|