e5d6ed68fd
The commit adds the following: - Adds tcgen05.ld.red Op with tests under tcgen05-ld-red.mlir and tcgen05-ld-red-invalid.mlir - Renamed ReduxKind to ReductionKind and renamed it across NVVM and GPU Dialects - Replaced Tcgen05LdRedOperationAtr with ReductionKindAttr - Updated tcgen05.ld.red and nvvm.redux.sync tests
554 lines
22 KiB
C++
554 lines
22 KiB
C++
//===- NVVMToLLVMIRTranslation.cpp - Translate NVVM to LLVM IR ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a translation between the MLIR NVVM dialect and
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// LLVM IR.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/IR/Operation.h"
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#include "mlir/Target/LLVMIR/ModuleTranslation.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/IntrinsicsNVPTX.h"
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#include "llvm/Support/FormatVariadic.h"
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using namespace mlir;
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using namespace mlir::LLVM;
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using mlir::LLVM::detail::createIntrinsicCall;
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#define REDUX_F32_ID_IMPL(op, abs, hasNaN) \
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hasNaN ? llvm::Intrinsic::nvvm_redux_sync_f##op##abs##_NaN \
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: llvm::Intrinsic::nvvm_redux_sync_f##op##abs
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#define GET_REDUX_F32_ID(op, hasAbs, hasNaN) \
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hasAbs ? REDUX_F32_ID_IMPL(op, _abs, hasNaN) : REDUX_F32_ID_IMPL(op, , hasNaN)
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static llvm::Intrinsic::ID getReduxIntrinsicId(llvm::Type *resultType,
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NVVM::ReductionKind kind,
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bool hasAbs, bool hasNaN) {
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switch (kind) {
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case NVVM::ReductionKind::ADD:
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return llvm::Intrinsic::nvvm_redux_sync_add;
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case NVVM::ReductionKind::UMAX:
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return llvm::Intrinsic::nvvm_redux_sync_umax;
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case NVVM::ReductionKind::UMIN:
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return llvm::Intrinsic::nvvm_redux_sync_umin;
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case NVVM::ReductionKind::AND:
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return llvm::Intrinsic::nvvm_redux_sync_and;
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case NVVM::ReductionKind::OR:
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return llvm::Intrinsic::nvvm_redux_sync_or;
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case NVVM::ReductionKind::XOR:
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return llvm::Intrinsic::nvvm_redux_sync_xor;
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case NVVM::ReductionKind::MAX:
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return llvm::Intrinsic::nvvm_redux_sync_max;
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case NVVM::ReductionKind::MIN:
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return llvm::Intrinsic::nvvm_redux_sync_min;
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case NVVM::ReductionKind::FMIN:
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return GET_REDUX_F32_ID(min, hasAbs, hasNaN);
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case NVVM::ReductionKind::FMAX:
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return GET_REDUX_F32_ID(max, hasAbs, hasNaN);
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}
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llvm_unreachable("unknown reduction kind");
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}
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static llvm::Intrinsic::ID getShflIntrinsicId(llvm::Type *resultType,
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NVVM::ShflKind kind,
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bool withPredicate) {
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if (withPredicate) {
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resultType = cast<llvm::StructType>(resultType)->getElementType(0);
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switch (kind) {
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case NVVM::ShflKind::bfly:
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return resultType->isFloatTy()
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? llvm::Intrinsic::nvvm_shfl_sync_bfly_f32p
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: llvm::Intrinsic::nvvm_shfl_sync_bfly_i32p;
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case NVVM::ShflKind::up:
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return resultType->isFloatTy() ? llvm::Intrinsic::nvvm_shfl_sync_up_f32p
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: llvm::Intrinsic::nvvm_shfl_sync_up_i32p;
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case NVVM::ShflKind::down:
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return resultType->isFloatTy()
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? llvm::Intrinsic::nvvm_shfl_sync_down_f32p
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: llvm::Intrinsic::nvvm_shfl_sync_down_i32p;
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case NVVM::ShflKind::idx:
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return resultType->isFloatTy() ? llvm::Intrinsic::nvvm_shfl_sync_idx_f32p
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: llvm::Intrinsic::nvvm_shfl_sync_idx_i32p;
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}
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} else {
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switch (kind) {
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case NVVM::ShflKind::bfly:
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return resultType->isFloatTy() ? llvm::Intrinsic::nvvm_shfl_sync_bfly_f32
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: llvm::Intrinsic::nvvm_shfl_sync_bfly_i32;
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case NVVM::ShflKind::up:
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return resultType->isFloatTy() ? llvm::Intrinsic::nvvm_shfl_sync_up_f32
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: llvm::Intrinsic::nvvm_shfl_sync_up_i32;
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case NVVM::ShflKind::down:
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return resultType->isFloatTy() ? llvm::Intrinsic::nvvm_shfl_sync_down_f32
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: llvm::Intrinsic::nvvm_shfl_sync_down_i32;
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case NVVM::ShflKind::idx:
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return resultType->isFloatTy() ? llvm::Intrinsic::nvvm_shfl_sync_idx_f32
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: llvm::Intrinsic::nvvm_shfl_sync_idx_i32;
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}
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}
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llvm_unreachable("unknown shuffle kind");
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}
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static llvm::Intrinsic::ID getMatchSyncIntrinsicId(Type valType,
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NVVM::MatchSyncKind kind) {
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switch (kind) {
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case NVVM::MatchSyncKind::any:
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return valType.isInteger(32) ? llvm::Intrinsic::nvvm_match_any_sync_i32
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: llvm::Intrinsic::nvvm_match_any_sync_i64;
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case NVVM::MatchSyncKind::all:
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// match.all instruction has two variants -- one returns a single value,
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// another returns a pair {value, predicate}. We currently only implement
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// the latter as that's the variant exposed by CUDA API.
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return valType.isInteger(32) ? llvm::Intrinsic::nvvm_match_all_sync_i32p
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: llvm::Intrinsic::nvvm_match_all_sync_i64p;
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}
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llvm_unreachable("unsupported match sync kind");
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}
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static llvm::Intrinsic::ID getVoteSyncIntrinsicId(NVVM::VoteSyncKind kind) {
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switch (kind) {
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case NVVM::VoteSyncKind::any:
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return llvm::Intrinsic::nvvm_vote_any_sync;
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case NVVM::VoteSyncKind::all:
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return llvm::Intrinsic::nvvm_vote_all_sync;
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case NVVM::VoteSyncKind::ballot:
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return llvm::Intrinsic::nvvm_vote_ballot_sync;
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case NVVM::VoteSyncKind::uni:
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return llvm::Intrinsic::nvvm_vote_uni_sync;
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}
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llvm_unreachable("unsupported vote kind");
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}
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static llvm::Intrinsic::ID
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getLdMatrixIntrinsicId(NVVM::MMALayout layout, int32_t num,
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NVVM::LdStMatrixShapeAttr shape,
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NVVM::LdStMatrixEltType eltType) {
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if (shape.getM() == 8 && shape.getN() == 8) {
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switch (num) {
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case 1:
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return (layout == NVVM::MMALayout::row)
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? llvm::Intrinsic::nvvm_ldmatrix_sync_aligned_m8n8_x1_b16
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: llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16;
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case 2:
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return (layout == NVVM::MMALayout::row)
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? llvm::Intrinsic::nvvm_ldmatrix_sync_aligned_m8n8_x2_b16
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: llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16;
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case 4:
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return (layout == NVVM::MMALayout::row)
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? llvm::Intrinsic::nvvm_ldmatrix_sync_aligned_m8n8_x4_b16
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: llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16;
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}
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} else if (shape.getM() == 8 && shape.getN() == 16) {
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if (eltType == NVVM::LdStMatrixEltType::B8X16_B6X16_P32) {
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switch (num) {
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case 1:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n16_x1_b8x16_b6x16_p32;
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case 2:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n16_x2_b8x16_b6x16_p32;
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case 4:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n16_x4_b8x16_b6x16_p32;
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}
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} else if (eltType == NVVM::LdStMatrixEltType::B8X16_B4X16_P64) {
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switch (num) {
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case 1:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n16_x1_b8x16_b4x16_p64;
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case 2:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n16_x2_b8x16_b4x16_p64;
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case 4:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m8n16_x4_b8x16_b4x16_p64;
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}
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}
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} else if (shape.getM() == 16 && shape.getN() == 16) {
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if (eltType == NVVM::LdStMatrixEltType::B8) {
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switch (num) {
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case 1:
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return llvm::Intrinsic::nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8;
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case 2:
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return llvm::Intrinsic::nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8;
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}
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} else if (eltType == NVVM::LdStMatrixEltType::B8X16_B6X16_P32) {
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switch (num) {
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case 1:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8x16_b6x16_p32;
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case 2:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8x16_b6x16_p32;
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}
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} else if (eltType == NVVM::LdStMatrixEltType::B8X16_B4X16_P64) {
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switch (num) {
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case 1:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8x16_b4x16_p64;
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case 2:
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return llvm::Intrinsic::
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nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8x16_b4x16_p64;
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}
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}
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}
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llvm_unreachable("unknown ldmatrix kind");
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}
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/// Return the intrinsic ID associated with stmatrix for the given paramters.
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static llvm::Intrinsic::ID
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getStMatrixIntrinsicId(NVVM::MMALayout layout, int32_t num,
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NVVM::LdStMatrixShapeAttr shape,
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NVVM::LdStMatrixEltType eltType) {
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if (shape.getM() == 8 && shape.getN() == 8) {
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switch (num) {
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case 1:
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return (layout == NVVM::MMALayout::row)
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? llvm::Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x1_b16
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: llvm::Intrinsic::
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nvvm_stmatrix_sync_aligned_m8n8_x1_trans_b16;
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case 2:
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return (layout == NVVM::MMALayout::row)
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? llvm::Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x2_b16
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: llvm::Intrinsic::
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nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16;
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case 4:
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return (layout == NVVM::MMALayout::row)
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? llvm::Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x4_b16
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: llvm::Intrinsic::
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nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16;
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}
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} else if (shape.getM() == 16 && shape.getN() == 8) {
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switch (num) {
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case 1:
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return llvm::Intrinsic::nvvm_stmatrix_sync_aligned_m16n8_x1_trans_b8;
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case 2:
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return llvm::Intrinsic::nvvm_stmatrix_sync_aligned_m16n8_x2_trans_b8;
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case 4:
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return llvm::Intrinsic::nvvm_stmatrix_sync_aligned_m16n8_x4_trans_b8;
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}
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}
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llvm_unreachable("unknown stmatrix kind");
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}
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/// Return the intrinsic ID associated with st.bulk for the given address type.
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static llvm::Intrinsic::ID
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getStBulkIntrinsicId(LLVM::LLVMPointerType addrType) {
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bool isSharedMemory = addrType.getAddressSpace() ==
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static_cast<unsigned>(NVVM::NVVMMemorySpace::Shared);
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return isSharedMemory ? llvm::Intrinsic::nvvm_st_bulk_shared_cta
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: llvm::Intrinsic::nvvm_st_bulk;
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}
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static unsigned getUnidirectionalFenceProxyID(NVVM::ProxyKind fromProxy,
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NVVM::ProxyKind toProxy,
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NVVM::MemScopeKind scope,
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bool isRelease) {
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if (fromProxy == NVVM::ProxyKind::GENERIC &&
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toProxy == NVVM::ProxyKind::TENSORMAP) {
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switch (scope) {
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case NVVM::MemScopeKind::CTA: {
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if (isRelease)
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return llvm::Intrinsic::nvvm_fence_proxy_tensormap_generic_release_cta;
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return llvm::Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_cta;
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}
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case NVVM::MemScopeKind::CLUSTER: {
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if (isRelease)
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return llvm::Intrinsic::
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nvvm_fence_proxy_tensormap_generic_release_cluster;
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return llvm::Intrinsic::
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nvvm_fence_proxy_tensormap_generic_acquire_cluster;
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}
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case NVVM::MemScopeKind::GPU: {
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if (isRelease)
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return llvm::Intrinsic::nvvm_fence_proxy_tensormap_generic_release_gpu;
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return llvm::Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_gpu;
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}
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case NVVM::MemScopeKind::SYS: {
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if (isRelease)
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return llvm::Intrinsic::nvvm_fence_proxy_tensormap_generic_release_sys;
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return llvm::Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_sys;
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}
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}
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llvm_unreachable("Unknown scope for uni-directional fence.proxy operation");
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}
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llvm_unreachable("Unsupported proxy kinds");
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}
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static unsigned getMembarIntrinsicID(NVVM::MemScopeKind scope) {
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switch (scope) {
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case NVVM::MemScopeKind::CTA:
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return llvm::Intrinsic::nvvm_membar_cta;
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case NVVM::MemScopeKind::CLUSTER:
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return llvm::Intrinsic::nvvm_fence_sc_cluster;
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case NVVM::MemScopeKind::GPU:
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return llvm::Intrinsic::nvvm_membar_gl;
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case NVVM::MemScopeKind::SYS:
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return llvm::Intrinsic::nvvm_membar_sys;
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}
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llvm_unreachable("Unknown scope for memory barrier");
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}
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#define TCGEN05LD(SHAPE, NUM) llvm::Intrinsic::nvvm_tcgen05_ld_##SHAPE##_##NUM
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static llvm::Intrinsic::ID
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getTcgen05LdIntrinsicID(mlir::NVVM::Tcgen05LdStShape shape, uint32_t num) {
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llvm::Intrinsic::ID Shape16x64b[] = {
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TCGEN05LD(16x64b, x1), TCGEN05LD(16x64b, x2), TCGEN05LD(16x64b, x4),
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TCGEN05LD(16x64b, x8), TCGEN05LD(16x64b, x16), TCGEN05LD(16x64b, x32),
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TCGEN05LD(16x64b, x64), TCGEN05LD(16x64b, x128),
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};
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llvm::Intrinsic::ID Shape16x128b[] = {
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TCGEN05LD(16x128b, x1), TCGEN05LD(16x128b, x2), TCGEN05LD(16x128b, x4),
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TCGEN05LD(16x128b, x8), TCGEN05LD(16x128b, x16), TCGEN05LD(16x128b, x32),
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TCGEN05LD(16x128b, x64),
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};
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llvm::Intrinsic::ID Shape16x256b[] = {
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TCGEN05LD(16x256b, x1), TCGEN05LD(16x256b, x2), TCGEN05LD(16x256b, x4),
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TCGEN05LD(16x256b, x8), TCGEN05LD(16x256b, x16), TCGEN05LD(16x256b, x32),
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};
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llvm::Intrinsic::ID Shape16x32bx2[] = {
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TCGEN05LD(16x32bx2, x1), TCGEN05LD(16x32bx2, x2),
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TCGEN05LD(16x32bx2, x4), TCGEN05LD(16x32bx2, x8),
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TCGEN05LD(16x32bx2, x16), TCGEN05LD(16x32bx2, x32),
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TCGEN05LD(16x32bx2, x64), TCGEN05LD(16x32bx2, x128),
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};
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llvm::Intrinsic::ID Shape32x32b[] = {
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TCGEN05LD(32x32b, x1), TCGEN05LD(32x32b, x2), TCGEN05LD(32x32b, x4),
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TCGEN05LD(32x32b, x8), TCGEN05LD(32x32b, x16), TCGEN05LD(32x32b, x32),
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TCGEN05LD(32x32b, x64), TCGEN05LD(32x32b, x128),
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};
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// `num` contains the length of vector and log2 of `num` returns the index
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// into the shape array
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unsigned Idx = std::log2(num);
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switch (shape) {
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case NVVM::Tcgen05LdStShape::SHAPE_16X64B:
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return Shape16x64b[Idx];
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case NVVM::Tcgen05LdStShape::SHAPE_16X128B:
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return Shape16x128b[Idx - 1];
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case NVVM::Tcgen05LdStShape::SHAPE_16X256B:
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return Shape16x256b[Idx - 2];
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case NVVM::Tcgen05LdStShape::SHAPE_32X32B:
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return Shape32x32b[Idx];
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case NVVM::Tcgen05LdStShape::SHAPE_16X32BX2:
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return Shape16x32bx2[Idx];
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}
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llvm_unreachable("unhandled tcgen05.ld lowering");
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}
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#define TCGEN05ST(SHAPE, NUM) llvm::Intrinsic::nvvm_tcgen05_st_##SHAPE##_##NUM
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static llvm::Intrinsic::ID
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getTcgen05StIntrinsicID(mlir::NVVM::Tcgen05LdStShape shape, uint32_t num) {
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llvm::Intrinsic::ID Shape16x64b[] = {
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TCGEN05ST(16x64b, x1), TCGEN05ST(16x64b, x2), TCGEN05ST(16x64b, x4),
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TCGEN05ST(16x64b, x8), TCGEN05ST(16x64b, x16), TCGEN05ST(16x64b, x32),
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TCGEN05ST(16x64b, x64), TCGEN05ST(16x64b, x128),
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};
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llvm::Intrinsic::ID Shape16x128b[] = {
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TCGEN05ST(16x128b, x1), TCGEN05ST(16x128b, x2), TCGEN05ST(16x128b, x4),
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TCGEN05ST(16x128b, x8), TCGEN05ST(16x128b, x16), TCGEN05ST(16x128b, x32),
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TCGEN05ST(16x128b, x64),
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};
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llvm::Intrinsic::ID Shape16x256b[] = {
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TCGEN05ST(16x256b, x1), TCGEN05ST(16x256b, x2), TCGEN05ST(16x256b, x4),
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TCGEN05ST(16x256b, x8), TCGEN05ST(16x256b, x16), TCGEN05ST(16x256b, x32),
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};
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|
|
|
llvm::Intrinsic::ID Shape16x32bx2[] = {
|
|
TCGEN05ST(16x32bx2, x1), TCGEN05ST(16x32bx2, x2),
|
|
TCGEN05ST(16x32bx2, x4), TCGEN05ST(16x32bx2, x8),
|
|
TCGEN05ST(16x32bx2, x16), TCGEN05ST(16x32bx2, x32),
|
|
TCGEN05ST(16x32bx2, x64), TCGEN05ST(16x32bx2, x128),
|
|
};
|
|
|
|
llvm::Intrinsic::ID Shape32x32b[] = {
|
|
TCGEN05ST(32x32b, x1), TCGEN05ST(32x32b, x2), TCGEN05ST(32x32b, x4),
|
|
TCGEN05ST(32x32b, x8), TCGEN05ST(32x32b, x16), TCGEN05ST(32x32b, x32),
|
|
TCGEN05ST(32x32b, x64), TCGEN05ST(32x32b, x128),
|
|
};
|
|
|
|
// `num` contains the length of vector and log2 of `num` returns the index
|
|
// into the shape array
|
|
unsigned Idx = std::log2(num);
|
|
|
|
switch (shape) {
|
|
case NVVM::Tcgen05LdStShape::SHAPE_16X64B:
|
|
return Shape16x64b[Idx];
|
|
case NVVM::Tcgen05LdStShape::SHAPE_16X128B:
|
|
return Shape16x128b[Idx - 1];
|
|
case NVVM::Tcgen05LdStShape::SHAPE_16X256B:
|
|
return Shape16x256b[Idx - 2];
|
|
case NVVM::Tcgen05LdStShape::SHAPE_32X32B:
|
|
return Shape32x32b[Idx];
|
|
case NVVM::Tcgen05LdStShape::SHAPE_16X32BX2:
|
|
return Shape16x32bx2[Idx];
|
|
}
|
|
llvm_unreachable("unhandled tcgen05.st lowering");
|
|
}
|
|
|
|
static llvm::Intrinsic::ID getFenceSyncRestrictID(NVVM::MemOrderKind order) {
|
|
return order == NVVM::MemOrderKind::ACQUIRE
|
|
? llvm::Intrinsic::
|
|
nvvm_fence_acquire_sync_restrict_space_cluster_scope_cluster
|
|
: llvm::Intrinsic::
|
|
nvvm_fence_release_sync_restrict_space_cta_scope_cluster;
|
|
}
|
|
|
|
static llvm::Intrinsic::ID
|
|
getFenceProxyID(NVVM::ProxyKind kind, std::optional<NVVM::SharedSpace> space) {
|
|
switch (kind) {
|
|
case NVVM::ProxyKind::alias:
|
|
return llvm::Intrinsic::nvvm_fence_proxy_alias;
|
|
case NVVM::ProxyKind::async:
|
|
return llvm::Intrinsic::nvvm_fence_proxy_async;
|
|
case NVVM::ProxyKind::async_global:
|
|
return llvm::Intrinsic::nvvm_fence_proxy_async_global;
|
|
case NVVM::ProxyKind::async_shared:
|
|
return *space == NVVM::SharedSpace::shared_cta
|
|
? llvm::Intrinsic::nvvm_fence_proxy_async_shared_cta
|
|
: llvm::Intrinsic::nvvm_fence_proxy_async_shared_cluster;
|
|
default:
|
|
llvm_unreachable("unsupported proxy kind");
|
|
}
|
|
}
|
|
|
|
static llvm::Intrinsic::ID
|
|
getFenceProxySyncRestrictID(NVVM::MemOrderKind order) {
|
|
return order == NVVM::MemOrderKind::ACQUIRE
|
|
? llvm::Intrinsic::
|
|
nvvm_fence_proxy_async_generic_acquire_sync_restrict_space_cluster_scope_cluster
|
|
: llvm::Intrinsic::
|
|
nvvm_fence_proxy_async_generic_release_sync_restrict_space_cta_scope_cluster;
|
|
}
|
|
|
|
namespace {
|
|
/// Implementation of the dialect interface that converts operations belonging
|
|
/// to the NVVM dialect to LLVM IR.
|
|
class NVVMDialectLLVMIRTranslationInterface
|
|
: public LLVMTranslationDialectInterface {
|
|
public:
|
|
using LLVMTranslationDialectInterface::LLVMTranslationDialectInterface;
|
|
|
|
/// Translates the given operation to LLVM IR using the provided IR builder
|
|
/// and saving the state in `moduleTranslation`.
|
|
LogicalResult
|
|
convertOperation(Operation *op, llvm::IRBuilderBase &builder,
|
|
LLVM::ModuleTranslation &moduleTranslation) const final {
|
|
Operation &opInst = *op;
|
|
#include "mlir/Dialect/LLVMIR/NVVMConversions.inc"
|
|
|
|
return failure();
|
|
}
|
|
|
|
/// Attaches module-level metadata for functions marked as kernels.
|
|
LogicalResult
|
|
amendOperation(Operation *op, ArrayRef<llvm::Instruction *> instructions,
|
|
NamedAttribute attribute,
|
|
LLVM::ModuleTranslation &moduleTranslation) const final {
|
|
auto func = dyn_cast<LLVM::LLVMFuncOp>(op);
|
|
if (!func)
|
|
return failure();
|
|
llvm::Function *llvmFunc = moduleTranslation.lookupFunction(func.getName());
|
|
|
|
if (attribute.getName() == NVVM::NVVMDialect::getMaxntidAttrName()) {
|
|
if (!isa<DenseI32ArrayAttr>(attribute.getValue()))
|
|
return failure();
|
|
auto values = cast<DenseI32ArrayAttr>(attribute.getValue());
|
|
const std::string attr = llvm::formatv(
|
|
"{0:$[,]}", llvm::make_range(values.asArrayRef().begin(),
|
|
values.asArrayRef().end()));
|
|
llvmFunc->addFnAttr("nvvm.maxntid", attr);
|
|
} else if (attribute.getName() == NVVM::NVVMDialect::getReqntidAttrName()) {
|
|
if (!isa<DenseI32ArrayAttr>(attribute.getValue()))
|
|
return failure();
|
|
auto values = cast<DenseI32ArrayAttr>(attribute.getValue());
|
|
const std::string attr = llvm::formatv(
|
|
"{0:$[,]}", llvm::make_range(values.asArrayRef().begin(),
|
|
values.asArrayRef().end()));
|
|
llvmFunc->addFnAttr("nvvm.reqntid", attr);
|
|
} else if (attribute.getName() ==
|
|
NVVM::NVVMDialect::getClusterDimAttrName()) {
|
|
if (!isa<DenseI32ArrayAttr>(attribute.getValue()))
|
|
return failure();
|
|
auto values = cast<DenseI32ArrayAttr>(attribute.getValue());
|
|
const std::string attr = llvm::formatv(
|
|
"{0:$[,]}", llvm::make_range(values.asArrayRef().begin(),
|
|
values.asArrayRef().end()));
|
|
llvmFunc->addFnAttr("nvvm.cluster_dim", attr);
|
|
} else if (attribute.getName() ==
|
|
NVVM::NVVMDialect::getClusterMaxBlocksAttrName()) {
|
|
auto value = dyn_cast<IntegerAttr>(attribute.getValue());
|
|
llvmFunc->addFnAttr("nvvm.maxclusterrank", llvm::utostr(value.getInt()));
|
|
} else if (attribute.getName() ==
|
|
NVVM::NVVMDialect::getMinctasmAttrName()) {
|
|
auto value = dyn_cast<IntegerAttr>(attribute.getValue());
|
|
llvmFunc->addFnAttr("nvvm.minctasm", llvm::utostr(value.getInt()));
|
|
} else if (attribute.getName() == NVVM::NVVMDialect::getMaxnregAttrName()) {
|
|
auto value = dyn_cast<IntegerAttr>(attribute.getValue());
|
|
llvmFunc->addFnAttr("nvvm.maxnreg", llvm::utostr(value.getInt()));
|
|
} else if (attribute.getName() ==
|
|
NVVM::NVVMDialect::getKernelFuncAttrName()) {
|
|
llvmFunc->setCallingConv(llvm::CallingConv::PTX_Kernel);
|
|
} else if (attribute.getName() ==
|
|
NVVM::NVVMDialect::getBlocksAreClustersAttrName()) {
|
|
llvmFunc->addFnAttr("nvvm.blocksareclusters");
|
|
}
|
|
|
|
return success();
|
|
}
|
|
|
|
LogicalResult
|
|
convertParameterAttr(LLVMFuncOp funcOp, int argIdx, NamedAttribute attribute,
|
|
LLVM::ModuleTranslation &moduleTranslation) const final {
|
|
|
|
llvm::LLVMContext &llvmContext = moduleTranslation.getLLVMContext();
|
|
llvm::Function *llvmFunc =
|
|
moduleTranslation.lookupFunction(funcOp.getName());
|
|
|
|
if (attribute.getName() == NVVM::NVVMDialect::getGridConstantAttrName()) {
|
|
llvmFunc->addParamAttr(
|
|
argIdx, llvm::Attribute::get(llvmContext, "nvvm.grid_constant"));
|
|
}
|
|
return success();
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
void mlir::registerNVVMDialectTranslation(DialectRegistry ®istry) {
|
|
registry.insert<NVVM::NVVMDialect>();
|
|
registry.addExtension(+[](MLIRContext *ctx, NVVM::NVVMDialect *dialect) {
|
|
dialect->addInterfaces<NVVMDialectLLVMIRTranslationInterface>();
|
|
});
|
|
}
|
|
|
|
void mlir::registerNVVMDialectTranslation(MLIRContext &context) {
|
|
DialectRegistry registry;
|
|
registerNVVMDialectTranslation(registry);
|
|
context.appendDialectRegistry(registry);
|
|
}
|