Krzysztof Drewniak 8c0e0d732f

[mlir][AMDGPU] Make AMDGPUToROCDL conversion tests use real address spaces (#180661) ...

Since #171876, -amdgpu-to-rocdl (the pass) is now set up to handle
address spaces like `#gpu.address_space<global>`. Update the tests
accordingly.

2026-02-09 18:18:07 -08:00

..

8-bit-floats-ocp.mlir

[mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs (#140801)

2025-05-21 13:50:02 -07:00

8-bit-floats.mlir

[mlir][ROCDL] Add fp4 and fp6 conversion intrinsics, fix fp8 immargs (#140801)

2025-05-21 13:50:02 -07:00

amdgpu-to-rocdl.mlir

[mlir][AMDGPU] Make AMDGPUToROCDL conversion tests use real address spaces (#180661)

2026-02-09 18:18:07 -08:00

dpp.mlir

…

gfx1250.mlir

[mlir][AMDGPU] Make AMDGPUToROCDL conversion tests use real address spaces (#180661)

2026-02-09 18:18:07 -08:00

load_lds-gfx950.mlir

[mlir][AMDGPU] Make AMDGPUToROCDL conversion tests use real address spaces (#180661)

2026-02-09 18:18:07 -08:00

load_lds.mlir

[mlir][AMDGPU] Make AMDGPUToROCDL conversion tests use real address spaces (#180661)

2026-02-09 18:18:07 -08:00

memory_counter_wait_tensor.mlir

[mlir][amdgpu] memory_counter_wait tensor counter support (#171153)

2025-12-08 20:02:40 +03:00

memory_counter_wait_unsupported.mlir

[mlir][amdgpu] memory_counter_wait tensor counter support (#171153)

2025-12-08 20:02:40 +03:00

memory_counter_wait.mlir

[mlir][amdgpu] memory_counter_wait tensor counter support (#171153)

2025-12-08 20:02:40 +03:00

mfma-gfx950.mlir

[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)

2026-01-21 21:50:25 +01:00

mfma.mlir

[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)

2026-01-21 21:50:25 +01:00

packed-ext.mlir

[mlir][AMDGPU] Add scaled floating point conversion ops (#141554)

2025-06-13 11:09:11 +02:00

packed-trunc.mlir

[mlir][AMDGPU] Add scaled floating point conversion ops (#141554)

2025-06-13 11:09:11 +02:00

permlane.mlir

[mlir][AMDGPU] Updated PermlaneSwapOp to select correct val (#157586)

2025-09-12 13:45:56 +02:00

sparse-mfma-gfx950.mlir

[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)

2026-01-21 21:50:25 +01:00

sparse-mfma.mlir

[ROCDL] Refactored MFMA ops in ODS; added constraints (#175775)

2026-01-21 21:50:25 +01:00

swizzle.mlir

[mlir] AMDGPUToROCDL: lower amdgpu.swizzle_bitmode (#136223)

2025-04-18 17:19:04 +03:00

transpose_load_reject.mlir

[AMDGPU] Adding AMDGPU dialect wrapper for ROCDL transpose loads. (#145395)

2025-06-25 22:58:14 -04:00

transpose_load.mlir

[AMDGPU] [MLIR] Add 96 and 128 bit GatherToLDS for gfx950 (#147496)

2025-07-09 11:53:26 -04:00

wmma-gfx11.mlir

[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands where possible (#167041)

2025-11-13 19:50:02 -05:00

wmma-gfx12.mlir

[mlir][ROCDL] Refactor wmma intrinsics to use attributes not operands where possible (#167041)

2025-11-13 19:50:02 -05:00

wmma-gfx1250.mlir

[mlir][AMDGPU] Add scaled wmma ops for gfx1250 (#169854)

2025-12-15 15:44:36 -08:00