9f422915c7
This PR re-lands https://github.com/llvm/llvm-project/pull/156830 This PR aims at fixing the nvdsl examples which got a bit out of sync not being tested in the CI. The fixed bugs were related to the following PRs: - move to nanobind #118583 - split gpu module initialization #135478 - gpu dialect python API change #163883
200 lines
11 KiB
Python
200 lines
11 KiB
Python
# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
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# RUN: sh -c 'if [[ "%mlir_run_cuda_sm90_tests" == "1" ]]; \
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# RUN: then %PYTHON %s | FileCheck %s; \
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# RUN: else export MLIR_NVDSL_PRINT_IR=1; \
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# RUN: %PYTHON %s | FileCheck %s --check-prefix=DUMPIR; fi'
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# ===----------------------------------------------------------------------===//
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# Chapter 3 : GEMM 128x128x64 with Tensor Core
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# ===----------------------------------------------------------------------===//
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#
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# This program demonstrates a GEMM operation with 128x128x64 matrix multiplication
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#
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# This chapter introduces demonstrates:
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# 1. Execute TMA Load for two input matrices
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# 2. Performs Tensor Core GEMM 128x128x64 by warpgroup
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# 3. Stores fragmented registers to global memory by warpgroup
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#
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# ===----------------------------------------------------------------------===//
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from mlir import ir
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from mlir.dialects import nvgpu, scf, arith, memref, vector, gpu
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from tools.nvdsl import *
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from mlir.extras import types as T
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import numpy as np
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def tma_load(
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mbar_group: Mbarriers,
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a_tma: TMA,
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b_tma: TMA,
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p,
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):
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"""
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TMA loads two input matrices from global memory to shared memory. It performs the following operations:
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- tma.load a_shared_memory[0] at coordinate [0, 0] (Loads 128x64)
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- tma.load b_shared_memory[0] at coordinate [0, 0] (Loads 64x64)
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- tma.load b_shared_memory[0] at coordinate [64, 0] (Loads 64x64)
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mbarrier.arrive ta_count = 128x64xf16 + 64x128xf16
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"""
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size_tma_a = get_type_size(a_tma.tma_memref)
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size_tma_b = get_type_size(b_tma.tma_memref)
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ta_count = size_tma_a + (size_tma_b * 2)
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off_b = size_tma_a
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off_b2 = off_b + size_tma_b
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a_elem_ty = a_tma.tma_memref.element_type
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b_elem_ty = b_tma.tma_memref.element_type
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a = get_dynamic_shared_memory(a_tma.tma_memref.shape, a_elem_ty)
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b1 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b)
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b2 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b2)
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mbar_group[0].arrive(ta_count, predicate=p)
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a_tma.load(a, mbar_group[0], coords=[0, 0], predicate=p)
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b_tma.load(b1, mbar_group[0], coords=[0, 0], predicate=p)
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b_tma.load(b2, mbar_group[0], coords=[64, 0], predicate=p)
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@NVDSL.mlir_func
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def gemm_128_128_64(a, b, d):
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token_ty = gpu.AsyncTokenType.get()
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t1 = gpu.wait([])
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a_dev, t2 = gpu.alloc(a.type, token_ty, [t1], [], [])
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b_dev, t3 = gpu.alloc(b.type, token_ty, [t2], [], [])
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d_dev, t4 = gpu.alloc(d.type, token_ty, [t3], [], [])
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t5 = gpu.memcpy(token_ty, [t4], a_dev, a)
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t6 = gpu.memcpy(token_ty, [t5], b_dev, b)
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t7 = gpu.wait([t6])
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sw = nvgpu.TensorMapSwizzleKind.SWIZZLE_128B
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a_tma = TMA([128, 64], a.type, swizzle=sw)
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b_tma = TMA([64, 64], b.type, swizzle=sw)
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a_tma.create_descriptor(a_dev)
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b_tma.create_descriptor(b_dev)
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a_size = get_type_size(a.type)
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b_size = get_type_size(b.type)
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smem_size_in_bytes = a_size + b_size
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@NVDSL.mlir_gpu_launch(grid=(1, 1, 1), block=(128, 1, 1), smem=smem_size_in_bytes)
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def gemm_tma_kernel():
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tidx = gpu.thread_id(gpu.Dimension.x)
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mbar_group = Mbarriers(number_of_barriers=1)
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isThread0 = tidx == 0
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mbar_group[0].init(1, predicate=isThread0)
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a_tma.prefetch(predicate=isThread0)
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b_tma.prefetch(predicate=isThread0)
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a_smem = get_dynamic_shared_memory((M, K), T.f16())
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b_smem = get_dynamic_shared_memory((K, N), T.f16(), offset=a_size)
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# 1. TMA Load for two input matrices
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tma_load(mbar_group, a_tma, b_tma, isThread0)
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# 2. All threads wait TMA load completion
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mbar_group[0].try_wait()
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# 3. Performs Tensor Core GEMM 128x128x64 by warpgroup
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A = WGMMAMatrix(WGMMAType.Descriptor, [M, K], desc=a_tma, smem=a_smem)
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B = WGMMAMatrix(WGMMAType.Descriptor, [K, N], desc=b_tma, smem=b_smem)
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D = WGMMAMatrix(WGMMAType.Accumulator, shape=[M, N], ty=T.f32())
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# Matrix Multiply
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D += A @ B
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# 4. Stores fragmented registers to global memory by warpgroup
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D.store_accumulator(d_dev)
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gemm_tma_kernel()
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t8 = gpu.memcpy(token_ty, [t7], d, d_dev)
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gpu.wait([t8])
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# Python pass arguments to MLIR
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M = 128
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N = 128
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K = 64
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a = np.random.randn(M, K).astype(np.float16)
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b = np.random.randn(K, N).astype(np.float16)
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d = np.zeros((M, N), np.float32)
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gemm_128_128_64(a, b, d)
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if os.getenv("MLIR_NVDSL_PRINT_IR") != "1":
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# Verify MLIR program with reference computation in python
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ref_d = a.astype(np.float16) @ b.astype(np.float16)
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np.testing.assert_allclose(d, ref_d, rtol=5e-03, atol=1e-01)
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print("PASS")
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# CHECK-NOT: Mismatched elements
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# CHECK: PASS
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# DUMPIR: func.func @gemm_128_128_64(%{{.*}}: memref<128x64xf16>, %{{.*}}: memref<64x128xf16>, %[[ARG2:.*]]: memref<128x128xf32>) attributes {llvm.emit_c_interface} {
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# DUMPIR: %[[C128:.*]] = arith.constant 128 : index
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# DUMPIR: %[[C64:.*]] = arith.constant 64 : index
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# DUMPIR: %[[TMA0:.*]] = nvgpu.tma.create.descriptor %{{.*}} box[%[[C128]], %[[C64]]] : memref<*xf16> -> <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
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# DUMPIR: %[[CAST1:.*]] = memref.cast %{{.*}} : memref<64x128xf16> to memref<*xf16>
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# DUMPIR: %[[C64_5:.*]] = arith.constant 64 : index
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# DUMPIR: %[[C64_6:.*]] = arith.constant 64 : index
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# DUMPIR: %[[TMA1:.*]] = nvgpu.tma.create.descriptor %[[CAST1]] box[%[[C64_5]], %[[C64_6]]] : memref<*xf16> -> <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
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# DUMPIR: %[[THREADID:.*]] = gpu.thread_id x
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# DUMPIR: %[[MB:.*]] = nvgpu.mbarrier.create -> <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0:.*]] = arith.constant 0 : index
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# DUMPIR: %[[EQ:.*]] = arith.cmpi eq, %[[THREADID]], %[[C0]] : index
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# DUMPIR: %[[C0_12:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C1_13:.*]] = arith.constant 1 : index
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# DUMPIR: nvgpu.mbarrier.init %[[MB]][%[[C0_12]]], %[[C1_13]], predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: nvgpu.tma.prefetch.descriptor %[[TMA0]], predicate = %[[EQ]] : <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
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# DUMPIR: nvgpu.tma.prefetch.descriptor %[[TMA1]], predicate = %[[EQ]] : <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>
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# DUMPIR: %[[DSM0:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_14:.*]] = arith.constant 0 : index
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# DUMPIR: %[[VIEW:.*]] = memref.view %[[DSM0]][%[[C0_14]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<128x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[DSM1:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C16384:.*]] = arith.constant 16384 : index
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# DUMPIR: %[[VIEW_15:.*]] = memref.view %[[DSM1]][%[[C16384]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<64x128xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[DSM2:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_16:.*]] = arith.constant 0 : index
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# DUMPIR: %[[VIEW_17:.*]] = memref.view %[[DSM2]][%[[C0_16]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<128x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[DSM3:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C16384_18:.*]] = arith.constant 16384 : index
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# DUMPIR: %[[VIEW_19:.*]] = memref.view %[[DSM3]][%[[C16384_18]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<64x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[DSM4:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C24576:.*]] = arith.constant 24576 : index
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# DUMPIR: %[[VIEW_20:.*]] = memref.view %[[DSM4]][%[[C24576]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<64x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_21:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C32768:.*]] = arith.constant 32768 : index
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# DUMPIR: nvgpu.mbarrier.arrive.expect_tx %[[MB]][%[[C0_21]]], %[[C32768]], predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_22:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_23:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_24:.*]] = arith.constant 0 : index
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# DUMPIR: nvgpu.tma.async.load %[[TMA0]][%[[C0_23]], %[[C0_24]]], %[[MB]][%[[C0_22]]] to %[[VIEW_17]], predicate = %[[EQ]] : <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<128x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_25:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_26:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C0_27:.*]] = arith.constant 0 : index
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# DUMPIR: nvgpu.tma.async.load %[[TMA1]][%[[C0_26]], %[[C0_27]]], %[[MB]][%[[C0_25]]] to %[[VIEW_19]], predicate = %[[EQ]] : <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<64x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_28:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C64_29:.*]] = arith.constant 64 : index
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# DUMPIR: %[[C0_30:.*]] = arith.constant 0 : index
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# DUMPIR: nvgpu.tma.async.load %[[TMA1]][%[[C64_29]], %[[C0_30]]], %[[MB]][%[[C0_28]]] to %[[VIEW_20]], predicate = %[[EQ]] : <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<64x64xf16, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_31:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C10000000:.*]] = arith.constant 10000000 : index
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# DUMPIR: %[[FALSE:.*]] = arith.constant false
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# DUMPIR: nvgpu.mbarrier.try_wait.parity %[[MB]][%[[C0_31]]], %[[FALSE]], %[[C10000000]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[WG_ACC:.*]] = nvgpu.warpgroup.mma.init.accumulator -> <fragmented = vector<128x128xf32>>
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# DUMPIR: %[[GEN0:.*]] = nvgpu.warpgroup.generate.descriptor %[[VIEW]], %[[TMA0]] : memref<128x64xf16, #gpu.address_space<workgroup>>, <tensor = memref<128x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none> -> <tensor = memref<128x64xf16, #gpu.address_space<workgroup>>>
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# DUMPIR: %[[GEN1:.*]] = nvgpu.warpgroup.generate.descriptor %[[VIEW_15]], %[[TMA1]] : memref<64x128xf16, #gpu.address_space<workgroup>>, <tensor = memref<64x64xf16, 3>, swizzle = swizzle_128b, l2promo = none, oob = zero, interleave = none> -> <tensor = memref<64x128xf16, #gpu.address_space<workgroup>>>
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# DUMPIR: %[[MMA:.*]] = nvgpu.warpgroup.mma %[[GEN0]], %[[GEN1]], %[[WG_ACC]] {transposeB} : <tensor = memref<128x64xf16, #gpu.address_space<workgroup>>>, <tensor = memref<64x128xf16, #gpu.address_space<workgroup>>>, <fragmented = vector<128x128xf32>> -> <fragmented = vector<128x128xf32>>
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# DUMPIR: nvgpu.warpgroup.mma.store %[[MMA]], %{{.*}} : <fragmented = vector<128x128xf32>> to memref<128x128xf32>
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# DUMPIR: gpu.terminator
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# DUMPIR: }
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# DUMPIR: %[[CPY3:.*]] = gpu.memcpy async [%{{.*}}] %[[ARG2]], %{{.*}} : memref<128x128xf32>, memref<128x128xf32>
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# DUMPIR: gpu.wait async [%[[CPY3]]]
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# DUMPIR: return
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# DUMPIR: }
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