9e6b2e1605
Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
152 lines
5.5 KiB
C++
152 lines
5.5 KiB
C++
//===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements RISCV TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
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static const char *const GCCRegNames[] = {
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// Integer registers
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
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"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
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// Floating point registers
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
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return llvm::makeArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
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static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
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{{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
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{{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
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{{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
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{{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
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{{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
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{{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
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{{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
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{{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"},
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{{"ft0"}, "f0"}, {{"ft1"}, "f1"}, {{"ft2"}, "f2"}, {{"ft3"}, "f3"},
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{{"ft4"}, "f4"}, {{"ft5"}, "f5"}, {{"ft6"}, "f6"}, {{"ft7"}, "f7"},
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{{"fs0"}, "f8"}, {{"fs1"}, "f9"}, {{"fa0"}, "f10"}, {{"fa1"}, "f11"},
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{{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"}, {{"fa5"}, "f15"},
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{{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"}, {{"fs3"}, "f19"},
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{{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"}, {{"fs7"}, "f23"},
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{{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"},
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{{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"}, "f31"}};
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return llvm::makeArrayRef(GCCRegAliases);
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}
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bool RISCVTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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switch (*Name) {
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default:
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return false;
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case 'I':
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// A 12-bit signed immediate.
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Info.setRequiresImmediate(-2048, 2047);
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return true;
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case 'J':
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// Integer zero.
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Info.setRequiresImmediate(0);
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return true;
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case 'K':
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// A 5-bit unsigned immediate for CSR access instructions.
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Info.setRequiresImmediate(0, 31);
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return true;
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case 'f':
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// A floating-point register.
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Info.setAllowsRegister();
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return true;
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}
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}
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void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__ELF__");
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Builder.defineMacro("__riscv");
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bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
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Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
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// TODO: modify when more code models are supported.
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Builder.defineMacro("__riscv_cmodel_medlow");
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StringRef ABIName = getABI();
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if (ABIName == "ilp32f" || ABIName == "lp64f")
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Builder.defineMacro("__riscv_float_abi_single");
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else if (ABIName == "ilp32d" || ABIName == "lp64d")
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Builder.defineMacro("__riscv_float_abi_double");
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else if (ABIName == "ilp32e")
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Builder.defineMacro("__riscv_abi_rve");
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else
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Builder.defineMacro("__riscv_float_abi_soft");
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if (HasM) {
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Builder.defineMacro("__riscv_mul");
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Builder.defineMacro("__riscv_div");
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Builder.defineMacro("__riscv_muldiv");
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}
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if (HasA)
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Builder.defineMacro("__riscv_atomic");
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if (HasF || HasD) {
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Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
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Builder.defineMacro("__riscv_fdiv");
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Builder.defineMacro("__riscv_fsqrt");
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}
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if (HasC)
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Builder.defineMacro("__riscv_compressed");
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}
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/// Return true if has this feature, need to sync with handleTargetFeatures.
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bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
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bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
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return llvm::StringSwitch<bool>(Feature)
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.Case("riscv", true)
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.Case("riscv32", !Is64Bit)
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.Case("riscv64", Is64Bit)
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.Case("m", HasM)
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.Case("a", HasA)
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.Case("f", HasF)
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.Case("d", HasD)
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.Case("c", HasC)
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.Default(false);
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}
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/// Perform initialization based on the user configured set of features.
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bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) {
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for (const auto &Feature : Features) {
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if (Feature == "+m")
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HasM = true;
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else if (Feature == "+a")
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HasA = true;
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else if (Feature == "+f")
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HasF = true;
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else if (Feature == "+d")
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HasD = true;
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else if (Feature == "+c")
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HasC = true;
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}
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return true;
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}
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