747620db2a
This PR adds the XeGPU workgroup (wg) to subgroup (sg) pass. The wg to sg pass transforms the xegpu wg level operations to subgroup operations based on the sg_layout and sg_data attribute. The PR adds transformation patterns for following Ops 1. CreateNdDesc 2. LoadNd 3. StoreNd 4. PrefetchNd 4. UpdateNdOffset 5. Dpas
379 lines
15 KiB
C++
379 lines
15 KiB
C++
//===- XeGPUWgToSgDistribute.cpp - XeGPU Workgroup to Subgroup Pass -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Dialect/XeGPU/Transforms/Passes.h"
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#include "mlir/Dialect/Affine/Utils.h"
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#include "mlir/Dialect/Arith/Utils/Utils.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/Index/IR/IndexDialect.h"
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#include "mlir/Dialect/Index/IR/IndexOps.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/Utils/IndexingUtils.h"
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#include "mlir/Dialect/XeGPU/IR/XeGPU.h"
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#include "mlir/Dialect/XeGPU/Transforms/Transforms.h"
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#include "mlir/Transforms/DialectConversion.h"
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namespace mlir {
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namespace xegpu {
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#define GEN_PASS_DEF_XEGPUWGTOSGDISTRIBUTE
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#include "mlir/Dialect/XeGPU/Transforms/Passes.h.inc"
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} // namespace xegpu
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} // namespace mlir
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using namespace mlir;
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namespace {
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/// This pattern transforms the CreateNdDescOp to create a subgroup descriptor
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/// from a workgroup descriptor. It replaces the offsets and sizes with
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/// appropriate values for the subgroup.
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/// It uses round-robin assignment to distribute the work to the subgroups.
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/// Following create_nd_desc operation:,
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/// %tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<24x24xf32>
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/// -> !xegpu.tensor_desc<24x24xf32, #xegpu.layout<sg_layout = [4, 4],
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/// sg_data = [2, 2], lane_layout = [2, 2], lane_data = [1, 1]>>
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/// is converted to 9 subgroup level operations based on the sg_layout &
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/// sg_data:
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/// %tdesc = xegpu.create_nd_tdesc %src[off1, off2] : memref<24x24xf32> ->
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/// !xegpu.tensor_desc<2x2xf32, #xegpu.layout<lane_layout = [2, 2],
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/// lane_data = [1, 1]>>
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///
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/// The sg_layout and sg_data attributes are dropped after the pass as they are
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/// no longer needed.
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///
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/// 24x24 matrix distribution example:
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/// sg_layout = [4, 4], sg_data = [2, 2]
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/// Each 8x8 matrix within the 24x24 matrix is called a distribution unit.
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/// dist_unit_shape = [8, 8] --> sg_layout[i] * sg_data[i]
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///
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/// +------------------------+
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/// | 8x8 | 8x8 | 8x8 | <- 3 tiles across
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/// |-----+-----+-----|
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/// | 8x8 | 8x8 | 8x8 | <- 3 tiles down
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/// |-----+-----+-----|
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/// | 8x8 | 8x8 | 8x8 |
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/// +------------------------+
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///
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/// Each 8x8 tile is further subdivided among subgroups:
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/// +------------------------+
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/// | 2x2 2x2 2x2 2x2 | <- 4 subgroups across (each handles 2 columns)
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/// | 2x2 2x2 2x2 2x2 | <- 4 subgroups down (each handles 2 rows)
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/// | 2x2 2x2 2x2 2x2 |
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/// | 2x2 2x2 2x2 2x2 |
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/// +------------------------+
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///
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/// Since the 24x24 matrix is divided into 8x8 distribution units, there will be
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/// 9 distribution units (3x3) in total. Hence the 9 subgroup level operations.
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/// The pass currently has entire distribution logic in the WgToSgCreateNdOp
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/// pattern and all the other ops just follow.
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/// TODO: Decouple the distribution logic from WgToSgCreateNdOp for all the
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/// ops in the pass.
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struct WgToSgCreateNdOp : public OpConversionPattern<xegpu::CreateNdDescOp> {
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using OpConversionPattern<xegpu::CreateNdDescOp>::OpConversionPattern;
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// Calculate offset for each subgroup
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SmallVector<OpFoldResult>
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calculateGlobalOffsets(ConversionPatternRewriter &rewriter, Location loc,
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const SmallVector<OpFoldResult> &originalOffsets,
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const SmallVector<Value> &localOffset,
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const SmallVector<int64_t> &distUnitBaseAddr,
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const SmallVector<int64_t> &distUnitShape) const {
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assert(localOffset.size() == distUnitBaseAddr.size() &&
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"localOffset and distUnitBaseAddr must have the same rank");
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SmallVector<OpFoldResult> globalOffsets(originalOffsets.begin(),
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originalOffsets.end());
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size_t rank = localOffset.size();
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for (size_t i = 0; i < rank; ++i) {
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size_t dimIdx = originalOffsets.size() - rank + i;
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Value constOffset =
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rewriter.create<arith::ConstantIndexOp>(loc, distUnitBaseAddr[i]);
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Value offset =
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rewriter.createOrFold<index::AddOp>(loc, localOffset[i], constOffset);
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Value modValue =
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rewriter.create<arith::ConstantIndexOp>(loc, distUnitShape[i]);
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Value offsetMod =
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rewriter.createOrFold<index::RemUOp>(loc, offset, modValue);
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Value origOffset = getValueOrCreateConstantIndexOp(
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rewriter, loc, originalOffsets[dimIdx]);
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Value globalOffset =
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rewriter.createOrFold<index::AddOp>(loc, origOffset, offsetMod);
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globalOffsets[dimIdx] = globalOffset;
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}
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return globalOffsets;
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}
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LogicalResult
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matchAndRewrite(xegpu::CreateNdDescOp op, OneToNOpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op.getLoc();
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MLIRContext *ctx = op.getContext();
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xegpu::TensorDescType tdescTy = op.getType();
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auto layout = dyn_cast<xegpu::LayoutAttr>(tdescTy.getLayout());
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if (!layout)
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return failure();
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Type elemTy = tdescTy.getElementType();
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ArrayRef<int64_t> wgShape = tdescTy.getShape();
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// sgLayout must be present for workgroup-level distribution.
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SmallVector<int64_t> sgLayout;
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if (auto sgLayoutAttr = layout.getSgLayout())
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sgLayout = llvm::to_vector_of<int64_t>(sgLayoutAttr.asArrayRef());
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else
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return rewriter.notifyMatchFailure(
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op, "sgLayout attribute is required in layout");
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SmallVector<int64_t> sgShape;
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if (auto sgDataAttr = layout.getSgData()) {
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sgShape = llvm::to_vector_of<int64_t>(sgDataAttr.asArrayRef());
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} else {
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assert(wgShape.size() == sgLayout.size() &&
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"sgLayout and wgShape must have the same rank");
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sgShape.reserve(wgShape.size());
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for (size_t i = 0; i < wgShape.size(); ++i) {
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assert(sgLayout[i] != 0 && "sgLayout elements must be non-zero");
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sgShape.push_back(wgShape[i] / sgLayout[i]);
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}
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}
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// TODO : Handle order attribute
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// Get the subgroup ID
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auto linearSgId =
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rewriter.create<gpu::SubgroupIdOp>(loc, /*upper_bound=*/nullptr);
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// Create constants for layout dimensions
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SmallVector<Value> sgLayoutDim(sgLayout.size());
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SmallVector<Value> sgDataDim(sgShape.size());
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for (size_t i = 0; i < sgLayout.size(); i++) {
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sgLayoutDim[i] =
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rewriter.create<arith::ConstantIndexOp>(loc, sgLayout[i]);
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sgDataDim[i] = rewriter.create<arith::ConstantIndexOp>(loc, sgShape[i]);
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}
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auto deLinearizeSgId =
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affine::delinearizeIndex(rewriter, loc, linearSgId, sgLayoutDim);
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if (failed(deLinearizeSgId))
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return failure();
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SmallVector<Value> sgIds = *deLinearizeSgId;
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// Calculate distribution unit shape and local offsets for subgroup
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SmallVector<int64_t> distUnitShape(sgLayout.size());
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SmallVector<Value> localOffset(sgLayout.size());
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for (size_t i = 0; i < sgLayout.size(); i++) {
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distUnitShape[i] = std::min(sgLayout[i] * sgShape[i], wgShape[i]);
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localOffset[i] =
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rewriter.createOrFold<index::MulOp>(loc, sgIds[i], sgDataDim[i]);
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}
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SmallVector<OpFoldResult> originalOffsets = op.getMixedOffsets();
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xegpu::TensorDescType newTdescTy =
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xegpu::TensorDescType::get(ctx, sgShape, elemTy, tdescTy.getEncoding(),
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layout.dropSgLayoutAndData());
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SmallVector<Value> newCreateNdOps;
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for (SmallVector<int64_t> distUnitBaseAddr :
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StaticTileOffsetRange(wgShape, distUnitShape)) {
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SmallVector<OpFoldResult> globalOffsets =
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calculateGlobalOffsets(rewriter, loc, originalOffsets, localOffset,
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distUnitBaseAddr, distUnitShape);
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auto newCreateNdOp = rewriter.create<xegpu::CreateNdDescOp>(
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loc, newTdescTy, op.getSource(), globalOffsets, op.getMixedSizes(),
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op.getMixedStrides());
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newCreateNdOps.push_back(newCreateNdOp);
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}
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rewriter.replaceOpWithMultiple(op, {newCreateNdOps});
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return success();
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}
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};
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/// This pattern transforms the LoadNdOp to load subgroup data.
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struct WgToSgLoadNdOp : public OpConversionPattern<xegpu::LoadNdOp> {
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using OpConversionPattern<xegpu::LoadNdOp>::OpConversionPattern;
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LogicalResult
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matchAndRewrite(xegpu::LoadNdOp op, OneToNOpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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SmallVector<Value> newLoadOps;
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for (auto src : adaptor.getTensorDesc()) {
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xegpu::TensorDescType tdescTy =
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dyn_cast<xegpu::TensorDescType>(src.getType());
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ArrayRef<int64_t> srcShape = tdescTy.getShape();
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VectorType newResTy = VectorType::get(srcShape, tdescTy.getElementType());
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auto newLoadOp = rewriter.create<xegpu::LoadNdOp>(op.getLoc(), newResTy,
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src, op->getAttrs());
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newLoadOps.push_back(newLoadOp);
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}
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rewriter.replaceOpWithMultiple(op, {newLoadOps});
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return mlir::success();
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}
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};
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/// This pattern transforms the StoreNdOp to store to a subgroup descriptor
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/// It creates a StoreNdOp op to store the updated values to the new subgroup
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/// src tensor descriptors.
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struct WgToSgStoreNdOp : public OpConversionPattern<xegpu::StoreNdOp> {
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using OpConversionPattern<xegpu::StoreNdOp>::OpConversionPattern;
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LogicalResult
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matchAndRewrite(xegpu::StoreNdOp op, OneToNOpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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for (auto [v, t] : llvm::zip(adaptor.getValue(), adaptor.getTensorDesc()))
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rewriter.create<xegpu::StoreNdOp>(op.getLoc(), v, t, op.getL1HintAttr(),
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op.getL2HintAttr(), op.getL3HintAttr());
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rewriter.eraseOp(op);
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return success();
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}
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};
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/// This pattern transforms the UpdateNdOffsetOp to update the offsets of a
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/// subgroup descriptor. It creates an UpdateNdOffsetOp op to update the
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/// offsets of the new subgroup src tensor descriptors.
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struct WgToSgUpdateNdOffsetOp
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: public OpConversionPattern<xegpu::UpdateNdOffsetOp> {
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using OpConversionPattern<xegpu::UpdateNdOffsetOp>::OpConversionPattern;
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LogicalResult
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matchAndRewrite(xegpu::UpdateNdOffsetOp op, OneToNOpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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llvm::SmallVector<Value> newUpdateTileOffsetOps;
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for (auto tDesc : adaptor.getTensorDesc()) {
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auto newUpdateTileOffsetOp = rewriter.create<xegpu::UpdateNdOffsetOp>(
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op.getLoc(), tDesc.getType(), tDesc, op.getOffsets(),
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op.getConstOffsets());
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newUpdateTileOffsetOps.push_back(newUpdateTileOffsetOp);
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}
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rewriter.replaceOpWithMultiple(op, {newUpdateTileOffsetOps});
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return success();
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}
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};
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/// This pattern transforms the DpasOp to work at subgroup level.
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struct WgToSgDpasOp : public OpConversionPattern<xegpu::DpasOp> {
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using OpConversionPattern<xegpu::DpasOp>::OpConversionPattern;
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LogicalResult
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matchAndRewrite(xegpu::DpasOp op, OneToNOpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op.getLoc();
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VectorType resultTy = op.getResult().getType();
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if (resultTy.getRank() != 2)
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return failure();
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auto originalLayout =
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llvm::dyn_cast_or_null<xegpu::LayoutAttr>(op->getAttr("layout"));
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if (!originalLayout)
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return failure();
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SmallVector<Value> newDpasOps;
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size_t i = 0;
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for (auto aVec : adaptor.getLhs()) {
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for (auto bVec : adaptor.getRhs()) {
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llvm::SmallVector<Value> operands({aVec, bVec});
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Value tmpC;
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if (op.getAcc()) {
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tmpC = adaptor.getAcc()[i++];
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operands.push_back(tmpC);
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}
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ArrayRef<int64_t> aVecShape =
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llvm::cast<VectorType>(aVec.getType()).getShape();
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ArrayRef<int64_t> bVecShape =
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llvm::cast<VectorType>(bVec.getType()).getShape();
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VectorType resTy = VectorType::get({aVecShape[0], bVecShape[1]},
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resultTy.getElementType());
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tmpC = rewriter.create<xegpu::DpasOp>(
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loc, resTy, operands,
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llvm::ArrayRef<NamedAttribute>(
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{"layout_result_0", originalLayout.dropSgLayoutAndData()}));
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newDpasOps.push_back(tmpC);
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}
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}
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rewriter.replaceOpWithMultiple(op, {newDpasOps});
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return success();
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}
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};
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/// This pattern transforms the PrefetchNdOp to prefetch the subgroup data.
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struct WgToSgPrefetchNdOp : public OpConversionPattern<xegpu::PrefetchNdOp> {
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using OpConversionPattern<xegpu::PrefetchNdOp>::OpConversionPattern;
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LogicalResult
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matchAndRewrite(xegpu::PrefetchNdOp op, OneToNOpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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for (auto src : adaptor.getTensorDesc())
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rewriter.create<xegpu::PrefetchNdOp>(op.getLoc(), TypeRange(), src,
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op->getAttrs());
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rewriter.eraseOp(op);
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return success();
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}
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};
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} // namespace
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namespace mlir {
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namespace xegpu {
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void populateXeGPUWgToSgDistributePatterns(RewritePatternSet &patterns) {
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patterns.add<WgToSgCreateNdOp, WgToSgLoadNdOp, WgToSgStoreNdOp,
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WgToSgUpdateNdOffsetOp, WgToSgDpasOp, WgToSgPrefetchNdOp>(
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patterns.getContext());
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}
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} // namespace xegpu
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} // namespace mlir
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namespace {
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struct XeGPUWgToSgDistributePass
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: public xegpu::impl::XeGPUWgToSgDistributeBase<XeGPUWgToSgDistributePass> {
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void runOnOperation() override;
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};
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} // namespace
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void XeGPUWgToSgDistributePass::runOnOperation() {
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MLIRContext *ctx = &getContext();
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RewritePatternSet patterns(ctx);
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ConversionTarget target(*ctx);
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auto getTensorDescType = [](Operation *op) -> xegpu::TensorDescType {
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if (auto createOp = dyn_cast<xegpu::CreateNdDescOp>(op))
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return createOp.getType();
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if (auto loadOp = dyn_cast<xegpu::LoadNdOp>(op))
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return loadOp.getTensorDescType();
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if (auto storeOp = dyn_cast<xegpu::StoreNdOp>(op))
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return storeOp.getTensorDescType();
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if (auto updateOp = dyn_cast<xegpu::UpdateNdOffsetOp>(op))
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return updateOp.getType();
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if (auto prefetchOp = dyn_cast<xegpu::PrefetchNdOp>(op))
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return prefetchOp.getTensorDescType();
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return xegpu::TensorDescType();
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};
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auto isLegal = [&](xegpu::LayoutAttr layout) -> bool {
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return !layout || layout.getSgLayout() == nullptr;
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};
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target.addDynamicallyLegalOp<xegpu::CreateNdDescOp, xegpu::LoadNdOp,
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xegpu::StoreNdOp, xegpu::UpdateNdOffsetOp,
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xegpu::PrefetchNdOp>([=](Operation *op) -> bool {
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auto tdescTy = getTensorDescType(op);
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auto layout = dyn_cast_or_null<xegpu::LayoutAttr>(tdescTy.getLayout());
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return isLegal(layout);
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});
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target.addDynamicallyLegalOp<xegpu::DpasOp>([=](xegpu::DpasOp op) -> bool {
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auto layout = dyn_cast_or_null<xegpu::LayoutAttr>(op->getAttr("layout"));
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return isLegal(layout);
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});
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target.markUnknownOpDynamicallyLegal([](Operation *) { return true; });
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xegpu::populateXeGPUWgToSgDistributePatterns(patterns);
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if (failed(
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applyPartialConversion(getOperation(), target, std::move(patterns))))
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return signalPassFailure();
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}
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