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llvm-project/llvm/test/CodeGen
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Stanislav Mekhanoshin 62fb3fa6d9 [AMDGPU] Define 6 dword subregs 
This prevents autogeneration of degenerate names for these.

Differential Revision: https://reviews.llvm.org/D80451
2020-05-22 13:53:29 -07:00
..
AArch64
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
AMDGPU
[AMDGPU] Define 6 dword subregs
2020-05-22 13:53:29 -07:00
ARC
…
ARM
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
AVR
[AVR] Fix I/O instructions on XMEGA
2020-05-17 19:46:09 +12:00
BPF
[BPF] Return fail if disassembled insn registers out of range
2020-05-18 18:53:23 -07:00
Generic
[MachineDebugify] Insert synthetic DBG_VALUE instructions
2020-04-22 17:03:39 -07:00
Hexagon
[ModuloSchedule] Fix epilogue peeling with illegal phi.
2020-05-07 10:04:05 -07:00
Inputs
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Lanai
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Mips
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
MIR
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
MSP430
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NVPTX
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
PowerPC
[NFC][AIX] Remove spaces after the comma for '.csect' directive
2020-05-22 11:10:32 -04:00
RISCV
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
SPARC
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SystemZ
[SystemZ] Eliminate the need to create a zero vector by reusing the VPERM mask.
2020-05-19 09:37:19 +02:00
Thumb
[ARM] Don't shrink STM if it would cause an unknown base register store
2020-04-22 14:50:42 +01:00
Thumb2
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
VE
[VE] Update branch instructions
2020-04-28 09:41:01 +02:00
WebAssembly
[WebAssembly] Fix bug in custom shuffle combine
2020-05-19 12:54:15 -07:00
WinCFGuard
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WinEH
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X86
Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias"
2020-05-22 21:26:46 +02:00
XCore
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