4e186f20e2
Fix a use-after-free issue related to annotateTableJump in the LoongArch target. Previously, `LoongArchPreRAExpandPseudo::annotateTableJump()` recorded a reference to a MachineOperand representing a jump table index. However, later optimizations such as the `BranchFolder` pass may delete the instruction containing this operand, leaving a dangling reference. This led to an assertion failure in `LoongArchAsmPrinter::emitJumpTableInfo()` when trying to access a freed MachineOperand via `getIndex()`. The fix avoids holding a reference to the MachineOperand. Instead, we extract and store the jump table index at the time of annotation. During `emitJumpTableInfo()`, we verify whether the recorded index still exists in the MachineFunction's jump table. If not, we skip emission for that entry. Fixes #140904
838 lines
31 KiB
C++
838 lines
31 KiB
C++
//===-- LoongArchExpandPseudoInsts.cpp - Expand pseudo instructions -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArch.h"
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#include "LoongArchInstrInfo.h"
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#include "LoongArchMachineFunctionInfo.h"
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#include "MCTargetDesc/LoongArchBaseInfo.h"
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#include "MCTargetDesc/LoongArchMCTargetDesc.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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extern cl::opt<bool> LArchAnnotateTableJump;
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#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME \
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"LoongArch Pre-RA pseudo instruction expansion pass"
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#define LOONGARCH_EXPAND_PSEUDO_NAME \
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"LoongArch pseudo instruction expansion pass"
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namespace {
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class LoongArchPreRAExpandPseudo : public MachineFunctionPass {
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public:
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const LoongArchInstrInfo *TII;
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static char ID;
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LoongArchPreRAExpandPseudo() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return LOONGARCH_PRERA_EXPAND_PSEUDO_NAME;
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}
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandPcalau12iInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode,
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unsigned FlagsLo);
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bool expandLargeAddressLoad(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LastOpcode, unsigned IdentifyingMO);
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bool expandLargeAddressLoad(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LastOpcode, unsigned IdentifyingMO,
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const MachineOperand &Symbol, Register DestReg,
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bool EraseFromParent);
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bool expandLoadAddressPcrel(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressGot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSLE(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadAddressTLSIE(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSLD(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSGD(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSDesc(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandFunctionCALL(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool IsTailCall);
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void annotateTableJump(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI);
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};
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char LoongArchPreRAExpandPseudo::ID = 0;
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bool LoongArchPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII =
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static_cast<const LoongArchInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool LoongArchPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool LoongArchPreRAExpandPseudo::expandMI(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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switch (MBBI->getOpcode()) {
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case LoongArch::PseudoLA_PCREL:
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return expandLoadAddressPcrel(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_PCREL_LARGE:
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return expandLoadAddressPcrel(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_GOT:
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return expandLoadAddressGot(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_GOT_LARGE:
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return expandLoadAddressGot(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_LE:
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return expandLoadAddressTLSLE(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_IE:
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return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_IE_LARGE:
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return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_LD:
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return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_LD_LARGE:
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return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_GD:
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return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_GD_LARGE:
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return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_DESC:
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return expandLoadAddressTLSDesc(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_DESC_LARGE:
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return expandLoadAddressTLSDesc(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoCALL:
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case LoongArch::PseudoCALL_LARGE:
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return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/false);
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case LoongArch::PseudoTAIL:
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case LoongArch::PseudoTAIL_LARGE:
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return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/true);
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case LoongArch::PseudoBRIND:
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// If the PseudoBRIND is used to table jump, then emit a label to annotate
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// the `jr` instruction, and save the instructions.
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if (LArchAnnotateTableJump)
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annotateTableJump(MBB, MBBI);
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break;
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}
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return false;
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}
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bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
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unsigned SecondOpcode, unsigned FlagsLo) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
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.addDisp(Symbol, 0, LoongArchII::encodeFlags(FlagsHi, EnableRelax));
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MachineInstr *SecondMI =
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BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
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.addReg(ScratchReg)
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.addDisp(Symbol, 0, LoongArchII::encodeFlags(FlagsLo, EnableRelax));
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if (MI.hasOneMemOperand())
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SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
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MI.eraseFromParent();
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return true;
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}
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bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
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unsigned IdentifyingMO) {
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MachineInstr &MI = *MBBI;
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LastOpcode, IdentifyingMO,
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MI.getOperand(2), MI.getOperand(0).getReg(),
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true);
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}
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bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
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unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg,
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bool EraseFromParent) {
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// Code Sequence:
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//
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// Part1: pcalau12i $scratch, %MO1(sym)
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// Part0: addi.d $dest, $zero, %MO0(sym)
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// Part2: lu32i.d $dest, %MO2(sym)
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// Part3: lu52i.d $dest, $dest, %MO3(sym)
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// Fin: LastOpcode $dest, $dest, $scratch
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unsigned MO0, MO1, MO2, MO3;
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switch (IdentifyingMO) {
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default:
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llvm_unreachable("unsupported identifying MO");
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case LoongArchII::MO_PCREL_LO:
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MO0 = IdentifyingMO;
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MO1 = LoongArchII::MO_PCREL_HI;
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MO2 = LoongArchII::MO_PCREL64_LO;
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MO3 = LoongArchII::MO_PCREL64_HI;
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break;
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case LoongArchII::MO_GOT_PC_HI:
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case LoongArchII::MO_LD_PC_HI:
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case LoongArchII::MO_GD_PC_HI:
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// These cases relocate just like the GOT case, except for Part1.
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MO0 = LoongArchII::MO_GOT_PC_LO;
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MO1 = IdentifyingMO;
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MO2 = LoongArchII::MO_GOT_PC64_LO;
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MO3 = LoongArchII::MO_GOT_PC64_HI;
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break;
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case LoongArchII::MO_IE_PC_LO:
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MO0 = IdentifyingMO;
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MO1 = LoongArchII::MO_IE_PC_HI;
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MO2 = LoongArchII::MO_IE_PC64_LO;
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MO3 = LoongArchII::MO_IE_PC64_HI;
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break;
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}
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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assert(MF->getSubtarget<LoongArchSubtarget>().is64Bit() &&
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"Large code model requires LA64");
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Register TmpPart1 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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Register TmpPart0 =
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DestReg.isVirtual()
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? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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Register TmpParts02 =
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DestReg.isVirtual()
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? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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Register TmpParts023 =
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DestReg.isVirtual()
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? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), TmpPart1);
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auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), TmpPart0)
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.addReg(LoongArch::R0);
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auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), TmpParts02)
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// "rj" is needed due to InstrInfo pattern requirement.
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.addReg(TmpPart0, RegState::Kill);
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auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), TmpParts023)
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.addReg(TmpParts02, RegState::Kill);
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BuildMI(MBB, MBBI, DL, TII->get(LastOpcode), DestReg)
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.addReg(TmpParts023)
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.addReg(TmpPart1, RegState::Kill);
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if (Symbol.getType() == MachineOperand::MO_ExternalSymbol) {
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const char *SymName = Symbol.getSymbolName();
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Part0.addExternalSymbol(SymName, MO0);
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Part1.addExternalSymbol(SymName, MO1);
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Part2.addExternalSymbol(SymName, MO2);
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Part3.addExternalSymbol(SymName, MO3);
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} else {
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Part0.addDisp(Symbol, 0, MO0);
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Part1.addDisp(Symbol, 0, MO1);
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Part2.addDisp(Symbol, 0, MO2);
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Part3.addDisp(Symbol, 0, MO3);
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}
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if (EraseFromParent)
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MI.eraseFromParent();
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return true;
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, bool Large) {
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if (Large)
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// Emit the 5-insn large address load sequence with the `%pc` family of
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// relocs.
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
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LoongArchII::MO_PCREL_LO);
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// Code Sequence:
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// pcalau12i $rd, %pc_hi20(sym)
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// addi.w/d $rd, $rd, %pc_lo12(sym)
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
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return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_PCREL_HI,
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SecondOpcode, LoongArchII::MO_PCREL_LO);
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, bool Large) {
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if (Large)
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// Emit the 5-insn large address load sequence with the `%got_pc` family
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// of relocs, loading the result from GOT with `ldx.d` in the end.
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
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LoongArchII::MO_GOT_PC_HI);
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// Code Sequence:
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// pcalau12i $rd, %got_pc_hi20(sym)
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// ld.w/d $rd, $rd, %got_pc_lo12(sym)
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
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return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_GOT_PC_HI,
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SecondOpcode, LoongArchII::MO_GOT_PC_LO);
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLE(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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// Code Sequence:
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// lu12i.w $rd, %le_hi20_r(sym)
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// add.w/d $rd, $rd, $tp, %le_add_r(sym)
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// addi.w/d $rd, $rd, %le_lo12_r(sym)
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//
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// Code Sequence while using the large code model:
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// lu12i.w $rd, %le_hi20(sym)
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// ori $rd, $rd, %le_lo12(sym)
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// lu32i.d $rd, %le64_lo20(sym)
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// lu52i.d $rd, $rd, %le64_hi12(sym)
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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bool Large = MF->getTarget().getCodeModel() == CodeModel::Large;
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Register DestReg = MI.getOperand(0).getReg();
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Register Parts01 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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Register Part1 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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if (!Large) {
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU12I_W), Part1)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_HI_R);
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned AddOp = STI.is64Bit() ? LoongArch::PseudoAddTPRel_D
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: LoongArch::PseudoAddTPRel_W;
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BuildMI(MBB, MBBI, DL, TII->get(AddOp), Parts01)
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.addReg(Part1, RegState::Kill)
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.addReg(LoongArch::R2)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_ADD_R);
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unsigned AddiOp = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
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BuildMI(MBB, MBBI, DL, TII->get(AddiOp), DestReg)
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.addReg(Parts01, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_LO_R);
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} else {
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU12I_W), Part1)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_HI);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ORI), Parts01)
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.addReg(Part1, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_LO);
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Register Parts012 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), Parts012)
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// "rj" is needed due to InstrInfo pattern requirement.
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.addReg(Parts01, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE64_LO);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), DestReg)
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.addReg(Parts012, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE64_HI);
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}
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MI.eraseFromParent();
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return true;
|
|
}
|
|
|
|
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool Large) {
|
|
if (Large)
|
|
// Emit the 5-insn large address load sequence with the `%ie_pc` family
|
|
// of relocs, loading the result with `ldx.d` in the end.
|
|
return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
|
|
LoongArchII::MO_IE_PC_LO);
|
|
|
|
// Code Sequence:
|
|
// pcalau12i $rd, %ie_pc_hi20(sym)
|
|
// ld.w/d $rd, $rd, %ie_pc_lo12(sym)
|
|
MachineFunction *MF = MBB.getParent();
|
|
const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
|
|
unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
|
|
return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_IE_PC_HI,
|
|
SecondOpcode, LoongArchII::MO_IE_PC_LO);
|
|
}
|
|
|
|
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool Large) {
|
|
if (Large)
|
|
// Emit the 5-insn large address load sequence with the `%got_pc` family
|
|
// of relocs, with the `pcalau12i` insn relocated with `%ld_pc_hi20`.
|
|
return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
|
|
LoongArchII::MO_LD_PC_HI);
|
|
|
|
// Code Sequence:
|
|
// pcalau12i $rd, %ld_pc_hi20(sym)
|
|
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
|
|
MachineFunction *MF = MBB.getParent();
|
|
const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
|
|
unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
|
|
return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_LD_PC_HI,
|
|
SecondOpcode, LoongArchII::MO_GOT_PC_LO);
|
|
}
|
|
|
|
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool Large) {
|
|
if (Large)
|
|
// Emit the 5-insn large address load sequence with the `%got_pc` family
|
|
// of relocs, with the `pcalau12i` insn relocated with `%gd_pc_hi20`.
|
|
return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
|
|
LoongArchII::MO_GD_PC_HI);
|
|
|
|
// Code Sequence:
|
|
// pcalau12i $rd, %gd_pc_hi20(sym)
|
|
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
|
|
MachineFunction *MF = MBB.getParent();
|
|
const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
|
|
unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
|
|
return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_GD_PC_HI,
|
|
SecondOpcode, LoongArchII::MO_GOT_PC_LO);
|
|
}
|
|
|
|
bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSDesc(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool Large) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
|
|
unsigned ADD = STI.is64Bit() ? LoongArch::ADD_D : LoongArch::ADD_W;
|
|
unsigned ADDI = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
|
|
unsigned LD = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
|
|
bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
|
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
|
Register Tmp1Reg =
|
|
MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
|
|
MachineOperand &Symbol = MI.getOperand(Large ? 2 : 1);
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), Tmp1Reg)
|
|
.addDisp(Symbol, 0,
|
|
LoongArchII::encodeFlags(LoongArchII::MO_DESC_PC_HI,
|
|
EnableRelax && !Large));
|
|
|
|
if (Large) {
|
|
// Code Sequence:
|
|
//
|
|
// pcalau12i $a0, %desc_pc_hi20(sym)
|
|
// addi.d $a1, $zero, %desc_pc_lo12(sym)
|
|
// lu32i.d $a1, %desc64_pc_lo20(sym)
|
|
// lu52i.d $a1, $a1, %desc64_pc_hi12(sym)
|
|
// add.d $a0, $a0, $a1
|
|
// ld.d $ra, $a0, %desc_ld(sym)
|
|
// jirl $ra, $ra, %desc_call(sym)
|
|
// add.d $dst, $a0, $tp
|
|
assert(MBB.getParent()->getSubtarget<LoongArchSubtarget>().is64Bit() &&
|
|
"Large code model requires LA64");
|
|
Register Tmp2Reg =
|
|
MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
|
|
Register Tmp3Reg =
|
|
MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
|
|
Register Tmp4Reg =
|
|
MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), Tmp2Reg)
|
|
.addReg(LoongArch::R0)
|
|
.addDisp(Symbol, 0, LoongArchII::MO_DESC_PC_LO);
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), Tmp3Reg)
|
|
.addReg(Tmp2Reg, RegState::Kill)
|
|
.addDisp(Symbol, 0, LoongArchII::MO_DESC64_PC_LO);
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), Tmp4Reg)
|
|
.addReg(Tmp3Reg)
|
|
.addDisp(Symbol, 0, LoongArchII::MO_DESC64_PC_HI);
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADD_D), LoongArch::R4)
|
|
.addReg(Tmp1Reg)
|
|
.addReg(Tmp4Reg);
|
|
} else {
|
|
// Code Sequence:
|
|
// pcalau12i $a0, %desc_pc_hi20(sym)
|
|
// addi.w/d $a0, $a0, %desc_pc_lo12(sym)
|
|
// ld.w/d $ra, $a0, %desc_ld(sym)
|
|
// jirl $ra, $ra, %desc_call(sym)
|
|
// add.w/d $dst, $a0, $tp
|
|
BuildMI(MBB, MBBI, DL, TII->get(ADDI), LoongArch::R4)
|
|
.addReg(Tmp1Reg)
|
|
.addDisp(
|
|
Symbol, 0,
|
|
LoongArchII::encodeFlags(LoongArchII::MO_DESC_PC_LO, EnableRelax));
|
|
}
|
|
|
|
BuildMI(MBB, MBBI, DL, TII->get(LD), LoongArch::R1)
|
|
.addReg(LoongArch::R4)
|
|
.addDisp(Symbol, 0,
|
|
LoongArchII::encodeFlags(LoongArchII::MO_DESC_LD,
|
|
EnableRelax && !Large));
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PseudoDESC_CALL), LoongArch::R1)
|
|
.addReg(LoongArch::R1)
|
|
.addDisp(Symbol, 0,
|
|
LoongArchII::encodeFlags(LoongArchII::MO_DESC_CALL,
|
|
EnableRelax && !Large));
|
|
BuildMI(MBB, MBBI, DL, TII->get(ADD), DestReg)
|
|
.addReg(LoongArch::R4)
|
|
.addReg(LoongArch::R2);
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
const MachineOperand &Func = MI.getOperand(0);
|
|
MachineInstrBuilder CALL;
|
|
unsigned Opcode;
|
|
|
|
switch (MF->getTarget().getCodeModel()) {
|
|
default:
|
|
report_fatal_error("Unexpected code model");
|
|
break;
|
|
case CodeModel::Small: {
|
|
// CALL:
|
|
// bl func
|
|
// TAIL:
|
|
// b func
|
|
Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
|
|
CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).add(Func);
|
|
break;
|
|
}
|
|
case CodeModel::Large: {
|
|
// Emit the 5-insn large address load sequence, either directly or
|
|
// indirectly in case of going through the GOT, then JIRL_TAIL or
|
|
// JIRL_CALL to $addr.
|
|
Opcode =
|
|
IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
|
|
Register AddrReg =
|
|
IsTailCall
|
|
? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
|
|
: LoongArch::R1;
|
|
|
|
bool UseGOT = Func.getTargetFlags() == LoongArchII::MO_CALL_PLT;
|
|
unsigned MO = UseGOT ? LoongArchII::MO_GOT_PC_HI : LoongArchII::MO_PCREL_LO;
|
|
unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
|
|
expandLargeAddressLoad(MBB, MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
|
|
false);
|
|
CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(AddrReg).addImm(0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Transfer implicit operands.
|
|
CALL.copyImplicitOps(MI);
|
|
|
|
// Transfer MI flags.
|
|
CALL.setMIFlags(MI.getFlags());
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
void LoongArchPreRAExpandPseudo::annotateTableJump(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
|
|
|
|
bool IsFound = false;
|
|
|
|
std::function<void(MachineInstr *, int)> FindJTIMI = [&](MachineInstr *MInst,
|
|
int FindDepth) {
|
|
if (FindDepth < 0)
|
|
return;
|
|
for (auto &MO : MInst->all_uses()) {
|
|
if (IsFound)
|
|
return;
|
|
Register Reg = MO.getReg();
|
|
if (!Reg.isVirtual())
|
|
continue;
|
|
MachineInstr *DefMI = MRI.getVRegDef(Reg);
|
|
if (!DefMI)
|
|
continue;
|
|
for (unsigned Idx = 0; Idx < DefMI->getNumOperands(); ++Idx) {
|
|
MachineOperand &MO = DefMI->getOperand(Idx);
|
|
if (MO.isJTI()) {
|
|
MBBI->setPreInstrSymbol(
|
|
*MF, MF->getContext().createNamedTempSymbol("jrtb_"));
|
|
MF->getInfo<LoongArchMachineFunctionInfo>()->setJumpInfo(
|
|
&*MBBI, MO.getIndex());
|
|
IsFound = true;
|
|
return;
|
|
}
|
|
}
|
|
FindJTIMI(DefMI, --FindDepth);
|
|
}
|
|
};
|
|
|
|
// FindDepth = 3, probably sufficient.
|
|
FindJTIMI(&*MBBI, /*FindDepth=*/3);
|
|
}
|
|
|
|
class LoongArchExpandPseudo : public MachineFunctionPass {
|
|
public:
|
|
const LoongArchInstrInfo *TII;
|
|
static char ID;
|
|
|
|
LoongArchExpandPseudo() : MachineFunctionPass(ID) {}
|
|
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
|
|
|
StringRef getPassName() const override {
|
|
return LOONGARCH_EXPAND_PSEUDO_NAME;
|
|
}
|
|
|
|
private:
|
|
bool expandMBB(MachineBasicBlock &MBB);
|
|
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandCopyCFR(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI);
|
|
bool expandFunctionCALL(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI,
|
|
bool IsTailCall);
|
|
};
|
|
|
|
char LoongArchExpandPseudo::ID = 0;
|
|
|
|
bool LoongArchExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
|
|
TII =
|
|
static_cast<const LoongArchInstrInfo *>(MF.getSubtarget().getInstrInfo());
|
|
|
|
bool Modified = false;
|
|
for (auto &MBB : MF)
|
|
Modified |= expandMBB(MBB);
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool LoongArchExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
while (MBBI != E) {
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
|
Modified |= expandMI(MBB, MBBI, NMBBI);
|
|
MBBI = NMBBI;
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool LoongArchExpandPseudo::expandMI(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
switch (MBBI->getOpcode()) {
|
|
case LoongArch::PseudoCopyCFR:
|
|
return expandCopyCFR(MBB, MBBI, NextMBBI);
|
|
case LoongArch::PseudoCALL_MEDIUM:
|
|
return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/false);
|
|
case LoongArch::PseudoTAIL_MEDIUM:
|
|
return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/true);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool LoongArchExpandPseudo::expandCopyCFR(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
|
|
// Expand:
|
|
// MBB:
|
|
// fcmp.caf.s $dst, $fa0, $fa0 # set $dst 0(false)
|
|
// bceqz $src, SinkBB
|
|
// FalseBB:
|
|
// fcmp.cueq.s $dst, $fa0, $fa0 # set $dst 1(true)
|
|
// SinkBB:
|
|
// fallthrough
|
|
|
|
const BasicBlock *LLVM_BB = MBB.getBasicBlock();
|
|
auto *FalseBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
auto *SinkBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MF->insert(++MBB.getIterator(), FalseBB);
|
|
MF->insert(++FalseBB->getIterator(), SinkBB);
|
|
|
|
Register DestReg = MI.getOperand(0).getReg();
|
|
Register SrcReg = MI.getOperand(1).getReg();
|
|
// DestReg = 0
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::SET_CFR_FALSE), DestReg);
|
|
// Insert branch instruction.
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::BCEQZ))
|
|
.addReg(SrcReg)
|
|
.addMBB(SinkBB);
|
|
// DestReg = 1
|
|
BuildMI(FalseBB, DL, TII->get(LoongArch::SET_CFR_TRUE), DestReg);
|
|
|
|
FalseBB->addSuccessor(SinkBB);
|
|
|
|
SinkBB->splice(SinkBB->end(), &MBB, MI, MBB.end());
|
|
SinkBB->transferSuccessors(&MBB);
|
|
|
|
MBB.addSuccessor(FalseBB);
|
|
MBB.addSuccessor(SinkBB);
|
|
|
|
NextMBBI = MBB.end();
|
|
MI.eraseFromParent();
|
|
|
|
// Make sure live-ins are correctly attached to this new basic block.
|
|
LivePhysRegs LiveRegs;
|
|
computeAndAddLiveIns(LiveRegs, *FalseBB);
|
|
computeAndAddLiveIns(LiveRegs, *SinkBB);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool LoongArchExpandPseudo::expandFunctionCALL(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
const MachineOperand &Func = MI.getOperand(0);
|
|
MachineInstrBuilder CALL;
|
|
unsigned Opcode;
|
|
|
|
switch (MF->getTarget().getCodeModel()) {
|
|
default:
|
|
report_fatal_error("Unexpected code model");
|
|
break;
|
|
case CodeModel::Medium: {
|
|
// CALL:
|
|
// pcaddu18i $ra, %call36(func)
|
|
// jirl $ra, $ra, 0
|
|
// TAIL:
|
|
// pcaddu18i $t8, %call36(func)
|
|
// jirl $r0, $t8, 0
|
|
Opcode =
|
|
IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
|
|
Register ScratchReg = IsTailCall ? LoongArch::R20 : LoongArch::R1;
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCADDU18I), ScratchReg);
|
|
|
|
CALL =
|
|
BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(ScratchReg).addImm(0);
|
|
|
|
if (Func.isSymbol())
|
|
MIB.addExternalSymbol(Func.getSymbolName(), LoongArchII::MO_CALL36);
|
|
else
|
|
MIB.addDisp(Func, 0, LoongArchII::MO_CALL36);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Transfer implicit operands.
|
|
CALL.copyImplicitOps(MI);
|
|
|
|
// Transfer MI flags.
|
|
CALL.setMIFlags(MI.getFlags());
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
} // end namespace
|
|
|
|
INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "loongarch-prera-expand-pseudo",
|
|
LOONGARCH_PRERA_EXPAND_PSEUDO_NAME, false, false)
|
|
|
|
INITIALIZE_PASS(LoongArchExpandPseudo, "loongarch-expand-pseudo",
|
|
LOONGARCH_EXPAND_PSEUDO_NAME, false, false)
|
|
|
|
namespace llvm {
|
|
|
|
FunctionPass *createLoongArchPreRAExpandPseudoPass() {
|
|
return new LoongArchPreRAExpandPseudo();
|
|
}
|
|
FunctionPass *createLoongArchExpandPseudoPass() {
|
|
return new LoongArchExpandPseudo();
|
|
}
|
|
|
|
} // end namespace llvm
|