be3fd6ae25
In some cases, such as using `lto` or `llc`, relax feature is not available from this `SubtargetInfo` (`LoongArchAsmBackend` is instantiated too early), causing loss of relocations. This commit modifiy the condition to check whether the section which contains the two symbols is relaxable. If not relaxable, no need to record relocations.
510 lines
18 KiB
C++
510 lines
18 KiB
C++
//===-- LoongArchAsmBackend.cpp - LoongArch Assembler Backend -*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LoongArchAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchAsmBackend.h"
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#include "LoongArchFixupKinds.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCSection.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/MathExtras.h"
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#define DEBUG_TYPE "loongarch-asmbackend"
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using namespace llvm;
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LoongArchAsmBackend::LoongArchAsmBackend(const MCSubtargetInfo &STI,
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uint8_t OSABI, bool Is64Bit,
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const MCTargetOptions &Options)
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: MCAsmBackend(llvm::endianness::little), STI(STI), OSABI(OSABI),
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Is64Bit(Is64Bit), TargetOptions(Options) {}
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std::optional<MCFixupKind>
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LoongArchAsmBackend::getFixupKind(StringRef Name) const {
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if (STI.getTargetTriple().isOSBinFormatELF()) {
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auto Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/LoongArch.def"
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#undef ELF_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_LARCH_NONE)
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.Case("BFD_RELOC_32", ELF::R_LARCH_32)
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.Case("BFD_RELOC_64", ELF::R_LARCH_64)
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.Default(-1u);
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if (Type != -1u)
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return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
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}
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return std::nullopt;
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}
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MCFixupKindInfo LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// LoongArchFixupKinds.h.
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//
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// {name, offset, bits, flags}
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{"fixup_loongarch_b16", 10, 16, 0},
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{"fixup_loongarch_b21", 0, 26, 0},
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{"fixup_loongarch_b26", 0, 26, 0},
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{"fixup_loongarch_abs_hi20", 5, 20, 0},
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{"fixup_loongarch_abs_lo12", 10, 12, 0},
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{"fixup_loongarch_abs64_lo20", 5, 20, 0},
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{"fixup_loongarch_abs64_hi12", 10, 12, 0},
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};
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static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
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"Not all fixup kinds added to Infos array");
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// Fixup kinds from .reloc directive are like R_LARCH_NONE. They
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// do not require any extra processing.
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if (mc::isRelocation(Kind))
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return {};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) <
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LoongArch::NumTargetFixupKinds &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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static void reportOutOfRangeError(MCContext &Ctx, SMLoc Loc, unsigned N) {
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Ctx.reportError(Loc, "fixup value out of range [" + Twine(llvm::minIntN(N)) +
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", " + Twine(llvm::maxIntN(N)) + "]");
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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switch (Fixup.getKind()) {
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default:
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llvm_unreachable("Unknown fixup kind");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case FK_Data_leb128:
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return Value;
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case LoongArch::fixup_loongarch_b16: {
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if (!isInt<18>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 18);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return (Value >> 2) & 0xffff;
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}
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case LoongArch::fixup_loongarch_b21: {
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if (!isInt<23>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 23);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x1f);
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}
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case LoongArch::fixup_loongarch_b26: {
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if (!isInt<28>(Value))
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reportOutOfRangeError(Ctx, Fixup.getLoc(), 28);
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if (Value % 4)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 4-byte aligned");
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return ((Value & 0x3fffc) << 8) | ((Value >> 18) & 0x3ff);
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}
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case LoongArch::fixup_loongarch_abs_hi20:
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return (Value >> 12) & 0xfffff;
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case LoongArch::fixup_loongarch_abs_lo12:
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return Value & 0xfff;
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case LoongArch::fixup_loongarch_abs64_lo20:
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return (Value >> 32) & 0xfffff;
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case LoongArch::fixup_loongarch_abs64_hi12:
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return (Value >> 52) & 0xfff;
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}
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}
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static void fixupLeb128(MCContext &Ctx, const MCFixup &Fixup, uint8_t *Data,
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uint64_t Value) {
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unsigned I;
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for (I = 0; Value; ++I, Value >>= 7)
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Data[I] |= uint8_t(Value & 0x7f);
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if (Value)
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Ctx.reportError(Fixup.getLoc(), "Invalid uleb128 value!");
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}
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void LoongArchAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
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const MCValue &Target, uint8_t *Data,
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uint64_t Value, bool IsResolved) {
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IsResolved = addReloc(F, Fixup, Target, Value, IsResolved);
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if (!Value)
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return; // Doesn't change encoding.
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auto Kind = Fixup.getKind();
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if (mc::isRelocation(Kind))
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return;
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MCFixupKindInfo Info = getFixupKindInfo(Kind);
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MCContext &Ctx = getContext();
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// Fixup leb128 separately.
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if (Fixup.getKind() == FK_Data_leb128)
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return fixupLeb128(Ctx, Fixup, Data, Value);
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// Apply any target-specific value adjustments.
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Value = adjustFixupValue(Fixup, Value, Ctx);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
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assert(Fixup.getOffset() + NumBytes <= F.getSize() &&
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"Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned I = 0; I != NumBytes; ++I) {
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Data[I] |= uint8_t((Value >> (I * 8)) & 0xff);
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}
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}
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static inline std::pair<MCFixupKind, MCFixupKind>
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getRelocPairForSize(unsigned Size) {
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switch (Size) {
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default:
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llvm_unreachable("unsupported fixup size");
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case 6:
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return std::make_pair(ELF::R_LARCH_ADD6, ELF::R_LARCH_SUB6);
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case 8:
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return std::make_pair(ELF::R_LARCH_ADD8, ELF::R_LARCH_SUB8);
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case 16:
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return std::make_pair(ELF::R_LARCH_ADD16, ELF::R_LARCH_SUB16);
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case 32:
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return std::make_pair(ELF::R_LARCH_ADD32, ELF::R_LARCH_SUB32);
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case 64:
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return std::make_pair(ELF::R_LARCH_ADD64, ELF::R_LARCH_SUB64);
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case 128:
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return std::make_pair(ELF::R_LARCH_ADD_ULEB128, ELF::R_LARCH_SUB_ULEB128);
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}
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}
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// Check if an R_LARCH_ALIGN relocation is needed for an alignment directive.
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// If conditions are met, compute the padding size and create a fixup encoding
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// the padding size in the addend. If MaxBytesToEmit is smaller than the padding
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// size, the fixup encodes MaxBytesToEmit in the higher bits and references a
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// per-section marker symbol.
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bool LoongArchAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) {
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// Alignments before the first linker-relaxable instruction have fixed sizes
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// and do not require relocations. Alignments after a linker-relaxable
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// instruction require a relocation, even if the STI specifies norelax.
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//
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// firstLinkerRelaxable is the layout order within the subsection, which may
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// be smaller than the section's order. Therefore, alignments in a
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// lower-numbered subsection may be unnecessarily treated as linker-relaxable.
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auto *Sec = F.getParent();
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if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable())
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return false;
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// Use default handling unless linker relaxation is enabled and the
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// MaxBytesToEmit >= the nop size.
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const unsigned MinNopLen = 4;
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unsigned MaxBytesToEmit = F.getAlignMaxBytesToEmit();
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if (MaxBytesToEmit < MinNopLen)
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return false;
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Size = F.getAlignment().value() - MinNopLen;
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if (F.getAlignment() <= MinNopLen)
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return false;
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MCContext &Ctx = getContext();
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const MCExpr *Expr = nullptr;
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if (MaxBytesToEmit >= Size) {
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Expr = MCConstantExpr::create(Size, getContext());
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} else {
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MCSection *Sec = F.getParent();
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const MCSymbolRefExpr *SymRef = getSecToAlignSym()[Sec];
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if (SymRef == nullptr) {
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// Define a marker symbol at the section with an offset of 0.
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MCSymbol *Sym = Ctx.createNamedTempSymbol("la-relax-align");
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Sym->setFragment(&*Sec->getBeginSymbol()->getFragment());
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Asm->registerSymbol(*Sym);
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SymRef = MCSymbolRefExpr::create(Sym, Ctx);
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getSecToAlignSym()[Sec] = SymRef;
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}
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Expr = MCBinaryExpr::createAdd(
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SymRef,
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MCConstantExpr::create((MaxBytesToEmit << 8) | Log2(F.getAlignment()),
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Ctx),
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Ctx);
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}
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MCFixup Fixup =
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MCFixup::create(0, Expr, FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN);
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F.setVarFixups({Fixup});
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F.setLinkerRelaxable();
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return true;
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}
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std::pair<bool, bool> LoongArchAsmBackend::relaxLEB128(MCFragment &F,
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int64_t &Value) const {
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const MCExpr &Expr = F.getLEBValue();
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if (F.isLEBSigned() || !Expr.evaluateKnownAbsolute(Value, *Asm))
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return std::make_pair(false, false);
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F.setVarFixups({MCFixup::create(0, &Expr, FK_Data_leb128)});
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return std::make_pair(true, true);
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}
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bool LoongArchAsmBackend::relaxDwarfLineAddr(MCFragment &F,
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bool &WasRelaxed) const {
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MCContext &C = getContext();
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int64_t LineDelta = F.getDwarfLineDelta();
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const MCExpr &AddrDelta = F.getDwarfAddrDelta();
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size_t OldSize = F.getVarSize();
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int64_t Value;
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if (AddrDelta.evaluateAsAbsolute(Value, *Asm))
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return false;
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[[maybe_unused]] bool IsAbsolute =
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AddrDelta.evaluateKnownAbsolute(Value, *Asm);
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assert(IsAbsolute);
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SmallVector<char> Data;
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raw_svector_ostream OS(Data);
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// INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
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if (LineDelta != INT64_MAX) {
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OS << uint8_t(dwarf::DW_LNS_advance_line);
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encodeSLEB128(LineDelta, OS);
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}
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// According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
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// takes a single unsigned half (unencoded) operand. The maximum encodable
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// value is therefore 65535. Set a conservative upper bound for relaxation.
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unsigned PCBytes;
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if (Value > 60000) {
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unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
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assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
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PCBytes = PtrSize;
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OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PtrSize + 1)
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<< uint8_t(dwarf::DW_LNE_set_address);
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OS.write_zeros(PtrSize);
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} else {
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PCBytes = 2;
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OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
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support::endian::write<uint16_t>(OS, 0, llvm::endianness::little);
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}
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auto Offset = OS.tell() - PCBytes;
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if (LineDelta == INT64_MAX) {
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OS << uint8_t(dwarf::DW_LNS_extended_op);
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OS << uint8_t(1);
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OS << uint8_t(dwarf::DW_LNE_end_sequence);
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} else {
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OS << uint8_t(dwarf::DW_LNS_copy);
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}
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F.setVarContents(Data);
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F.setVarFixups({MCFixup::create(Offset, &AddrDelta,
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MCFixup::getDataKindForSize(PCBytes))});
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WasRelaxed = OldSize != Data.size();
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return true;
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}
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bool LoongArchAsmBackend::relaxDwarfCFA(MCFragment &F, bool &WasRelaxed) const {
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const MCExpr &AddrDelta = F.getDwarfAddrDelta();
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SmallVector<MCFixup, 2> Fixups;
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size_t OldSize = F.getVarContents().size();
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int64_t Value;
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if (AddrDelta.evaluateAsAbsolute(Value, *Asm))
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return false;
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bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, *Asm);
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assert(IsAbsolute && "CFA with invalid expression");
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(void)IsAbsolute;
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assert(getContext().getAsmInfo()->getMinInstAlignment() == 1 &&
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"expected 1-byte alignment");
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if (Value == 0) {
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F.clearVarContents();
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F.clearVarFixups();
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WasRelaxed = OldSize != 0;
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return true;
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}
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auto AddFixups = [&Fixups,
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&AddrDelta](unsigned Offset,
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std::pair<MCFixupKind, MCFixupKind> FK) {
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const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
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Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(FK)));
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Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(FK)));
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};
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SmallVector<char, 8> Data;
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raw_svector_ostream OS(Data);
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if (isUIntN(6, Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc);
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AddFixups(0, getRelocPairForSize(6));
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} else if (isUInt<8>(Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc1);
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support::endian::write<uint8_t>(OS, 0, llvm::endianness::little);
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AddFixups(1, getRelocPairForSize(8));
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} else if (isUInt<16>(Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc2);
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support::endian::write<uint16_t>(OS, 0, llvm::endianness::little);
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AddFixups(1, getRelocPairForSize(16));
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} else if (isUInt<32>(Value)) {
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OS << uint8_t(dwarf::DW_CFA_advance_loc4);
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support::endian::write<uint32_t>(OS, 0, llvm::endianness::little);
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AddFixups(1, getRelocPairForSize(32));
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} else {
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llvm_unreachable("unsupported CFA encoding");
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}
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F.setVarContents(Data);
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F.setVarFixups(Fixups);
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WasRelaxed = OldSize != Data.size();
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return true;
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}
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bool LoongArchAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const {
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// We mostly follow binutils' convention here: align to 4-byte boundary with a
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// 0-fill padding.
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OS.write_zeros(Count % 4);
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// The remainder is now padded with 4-byte nops.
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// nop: andi r0, r0, 0
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for (; Count >= 4; Count -= 4)
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OS.write("\0\0\x40\x03", 4);
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return true;
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}
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bool LoongArchAsmBackend::isPCRelFixupResolved(const MCSymbol *SymA,
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const MCFragment &F) {
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// If the section does not contain linker-relaxable fragments, PC-relative
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// fixups can be resolved.
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if (!F.getParent()->isLinkerRelaxable())
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return true;
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// Otherwise, check if the offset between the symbol and fragment is fully
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// resolved, unaffected by linker-relaxable fragments (e.g. instructions or
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// offset-affected FT_Align fragments). Complements the generic
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// isSymbolRefDifferenceFullyResolvedImpl.
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if (!PCRelTemp)
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PCRelTemp = getContext().createTempSymbol();
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PCRelTemp->setFragment(const_cast<MCFragment *>(&F));
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MCValue Res;
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MCExpr::evaluateSymbolicAdd(Asm, false, MCValue::get(SymA),
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MCValue::get(nullptr, PCRelTemp), Res);
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return !Res.getSubSym();
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}
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bool LoongArchAsmBackend::addReloc(const MCFragment &F, const MCFixup &Fixup,
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const MCValue &Target, uint64_t &FixedValue,
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bool IsResolved) {
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auto Fallback = [&]() {
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MCAsmBackend::maybeAddReloc(F, Fixup, Target, FixedValue, IsResolved);
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return true;
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};
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uint64_t FixedValueA, FixedValueB;
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if (Target.getSubSym()) {
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assert(Target.getSpecifier() == 0 &&
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"relocatable SymA-SymB cannot have relocation specifier");
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std::pair<MCFixupKind, MCFixupKind> FK;
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const MCSymbol &SA = *Target.getAddSym();
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const MCSymbol &SB = *Target.getSubSym();
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bool force = !SA.isInSection() || !SB.isInSection();
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if (!force) {
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const MCSection &SecA = SA.getSection();
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const MCSection &SecB = SB.getSection();
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const MCSection &SecCur = *F.getParent();
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// To handle the case of A - B which B is same section with the current,
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// generate PCRel relocations is better than ADD/SUB relocation pair.
|
|
// We can resolve it as A - PC + PC - B. The A - PC will be resolved
|
|
// as a PCRel relocation, while PC - B will serve as the addend.
|
|
// If the linker relaxation is disabled, it can be done directly since
|
|
// PC - B is constant. Otherwise, we should evaluate whether PC - B
|
|
// is constant. If it can be resolved as PCRel, use Fallback which
|
|
// generates R_LARCH_{32,64}_PCREL relocation later.
|
|
if (&SecA != &SecB && &SecB == &SecCur &&
|
|
isPCRelFixupResolved(Target.getSubSym(), F))
|
|
return Fallback();
|
|
|
|
// In SecA == SecB case. If the section is not linker-relaxable, the
|
|
// FixedValue has already been calculated out in evaluateFixup,
|
|
// return true and avoid record relocations.
|
|
if (&SecA == &SecB && !SecA.isLinkerRelaxable())
|
|
return true;
|
|
}
|
|
|
|
switch (Fixup.getKind()) {
|
|
case llvm::FK_Data_1:
|
|
FK = getRelocPairForSize(8);
|
|
break;
|
|
case llvm::FK_Data_2:
|
|
FK = getRelocPairForSize(16);
|
|
break;
|
|
case llvm::FK_Data_4:
|
|
FK = getRelocPairForSize(32);
|
|
break;
|
|
case llvm::FK_Data_8:
|
|
FK = getRelocPairForSize(64);
|
|
break;
|
|
case llvm::FK_Data_leb128:
|
|
FK = getRelocPairForSize(128);
|
|
break;
|
|
default:
|
|
llvm_unreachable("unsupported fixup size");
|
|
}
|
|
MCValue A = MCValue::get(Target.getAddSym(), nullptr, Target.getConstant());
|
|
MCValue B = MCValue::get(Target.getSubSym());
|
|
auto FA = MCFixup::create(Fixup.getOffset(), nullptr, std::get<0>(FK));
|
|
auto FB = MCFixup::create(Fixup.getOffset(), nullptr, std::get<1>(FK));
|
|
Asm->getWriter().recordRelocation(F, FA, A, FixedValueA);
|
|
Asm->getWriter().recordRelocation(F, FB, B, FixedValueB);
|
|
FixedValue = FixedValueA - FixedValueB;
|
|
return false;
|
|
}
|
|
|
|
// If linker relaxation is enabled and supported by the current relocation,
|
|
// generate a relocation and then append a RELAX.
|
|
if (Fixup.isLinkerRelaxable())
|
|
IsResolved = false;
|
|
if (IsResolved && Fixup.isPCRel())
|
|
IsResolved = isPCRelFixupResolved(Target.getAddSym(), F);
|
|
|
|
if (!IsResolved)
|
|
Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);
|
|
|
|
if (Fixup.isLinkerRelaxable()) {
|
|
auto FA = MCFixup::create(Fixup.getOffset(), nullptr, ELF::R_LARCH_RELAX);
|
|
Asm->getWriter().recordRelocation(F, FA, MCValue::get(nullptr),
|
|
FixedValueA);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
std::unique_ptr<MCObjectTargetWriter>
|
|
LoongArchAsmBackend::createObjectTargetWriter() const {
|
|
return createLoongArchELFObjectWriter(OSABI, Is64Bit);
|
|
}
|
|
|
|
MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
|
|
const MCSubtargetInfo &STI,
|
|
const MCRegisterInfo &MRI,
|
|
const MCTargetOptions &Options) {
|
|
const Triple &TT = STI.getTargetTriple();
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
|
|
return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
|
|
}
|