llvm-project

AsmParser

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881 )

2025-01-23 10:14:25 +05:30

Disassembler

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881 )

2025-01-23 10:14:25 +05:30

GISel

[RISCV] GISel custom lowering for G_ADD/G_SUB (#121587 )

2025-01-07 18:53:10 -08:00

MCA

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MCTargetDesc

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881 )

2025-01-23 10:14:25 +05:30

TargetInfo

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CMakeLists.txt

[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866 )

2025-01-07 09:51:34 -08:00

RISCV.h

[RISCV] Introduce VLOptimizer pass (#108640 )

2024-10-11 09:45:35 -04:00

RISCV.td

[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866 )

2025-01-07 09:51:34 -08:00

RISCVAsmPrinter.cpp

[XRay][RISCV] RISCV support for XRay (#117368 )

2024-12-10 17:57:04 -08:00

RISCVCallingConv.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVCallingConv.h

[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503 )

2024-09-06 09:28:33 -07:00

RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVCombine.td

[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998 )

2025-01-02 16:29:34 -08:00

RISCVConstantPoolValue.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVConstantPoolValue.h

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778 )

2024-12-06 15:16:07 +05:30

RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (#113981 )

2024-10-28 22:37:47 -07:00

RISCVFeatures.td

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881 )

2025-01-23 10:14:25 +05:30

RISCVFrameLowering.cpp

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

RISCVFrameLowering.h

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

RISCVGatherScatterLowering.cpp

[RISCV] Allow non-loop invariant steps in RISCVGatherScatterLowering (#122244 )

2025-01-17 08:58:56 +08:00

RISCVGISel.td

[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729 )

2024-12-12 14:41:57 -08:00

RISCVIndirectBranchTracking.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV] Pass VSETVLIInfo by const reference. NFC

2025-01-03 16:51:08 -08:00

RISCVInsertWriteVXRM.cpp

[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044 )

2024-11-27 13:31:39 -08:00

RISCVInstrFormats.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022 )

2024-10-08 14:09:07 +01:00

RISCVInstrFormatsC.td

[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC

2025-01-10 14:28:54 -08:00

RISCVInstrFormatsV.td

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RISCVInstrGISel.td

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559 )

2024-11-11 20:59:21 -08:00

RISCVInstrInfo.cpp

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881 )

2025-01-23 10:14:25 +05:30

RISCVInstrInfo.h

[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) (#120622 )

2025-01-22 13:36:39 +05:30

RISCVInstrInfo.td

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

RISCVInstrInfoA.td

[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC

2024-12-17 10:24:50 -08:00

RISCVInstrInfoC.td

[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC

2025-01-10 14:28:54 -08:00

RISCVInstrInfoD.td

[RISCV][GISel] Support G_MERGE_VALUES/G_UNMERGE_VALUES with Zfa. (#120379 )

2025-01-07 07:50:50 -08:00

RISCVInstrInfoF.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoM.td

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RISCVInstrInfoSFB.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163 )

2024-10-29 21:23:31 -07:00

RISCVInstrInfoV.td

[RISCV][NFCI] Rationalize Immediate Definitions (#120718 )

2024-12-21 09:47:07 +00:00

RISCVInstrInfoVPseudos.td

[RISCV] Mark RVV stores and segmented loads as masked pseudo (#123106 )

2025-01-21 09:37:22 -08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787 )

2024-12-12 21:11:01 -08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787 )

2024-12-12 21:11:01 -08:00

RISCVInstrInfoXCV.td

[RISCV] Fix typo in CV_SH_rr_inc pattern (#120246 )

2024-12-17 12:20:17 -08:00

RISCVInstrInfoXqci.td

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881 )

2025-01-23 10:14:25 +05:30

RISCVInstrInfoXSf.td

[RISCV] Add @earlyclobber to SiFive custom matrix multiply instruction. (#124060 )

2025-01-23 08:26:39 -08:00

RISCVInstrInfoXTHead.td

[RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC

2024-12-29 12:44:33 -08:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

[RISCV][NFCI] Rationalize Immediate Definitions (#120718 )

2024-12-21 09:47:07 +00:00

RISCVInstrInfoZa.td

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RISCVInstrInfoZalasr.td

[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914 )

2024-12-17 00:19:45 -08:00

RISCVInstrInfoZb.td

[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221 )

2024-12-19 21:38:20 +01:00

RISCVInstrInfoZc.td

[RISCV] Simplify some RISCVInstrInfoC classes by removing arguments that never change. NFC

2025-01-09 16:21:55 -08:00

RISCVInstrInfoZcmop.td

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RISCVInstrInfoZfa.td

[RISCV] f32 roundeven pattern missed for Zfa (#118672 )

2024-12-04 13:52:20 -08:00

RISCVInstrInfoZfbfmin.td

[RISCV] Remove RISCVISD::FP_ROUND_BF16.

2024-09-03 20:18:01 -07:00

RISCVInstrInfoZfh.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

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RISCVInstrInfoZk.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279 )

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZvfbf.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

RISCVInstrInfoZvk.td

[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345 )

2025-01-22 07:42:27 +01:00

RISCVISelDAGToDAG.cpp

[RISCV] Select Zvkb VANDN for shorter constant loading sequences (#123345 )

2025-01-22 07:42:27 +01:00

RISCVISelDAGToDAG.h

[RISCV] Pattern-match frameindex (#120917 )

2024-12-23 13:19:00 +03:00

RISCVISelLowering.cpp

[RISCV][NFC] Remove Redundant Inline Asm Logic (#124202 )

2025-01-23 17:40:36 -08:00

RISCVISelLowering.h

[IA] Generalize the support for power-of-two (de)interleave intrinsics (#123863 )

2025-01-23 15:27:51 -08:00

RISCVLandingPadSetup.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVMachineFunctionInfo.cpp

[RISCV] Add stack clash protection (#117612 )

2024-12-10 16:48:26 +00:00

RISCVMachineFunctionInfo.h

[RISCV] Stack clash protection for dynamic alloca (#122508 )

2025-01-16 11:58:42 -08:00

RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVMergeBaseOffset.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

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RISCVPfmCounters.td

[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866 )

2025-01-07 09:51:34 -08:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.

2024-12-05 16:43:30 -08:00

RISCVProcessors.td

[RISCV] Add -mcpu=sifive-p550. (#122164 )

2025-01-08 21:02:46 -08:00

RISCVProfiles.td

[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942 )

2024-11-10 07:18:05 +00:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756 )

2024-12-06 14:07:27 -05:00

RISCVRegisterInfo.h

[RISCV] Correct the precedence in isVRegClass (#116579 )

2024-11-18 18:12:57 +08:00

RISCVRegisterInfo.td

[RISCV] Merge GPRPair and GPRF64Pair (#116094 )

2024-11-20 10:08:55 +00:00

RISCVSchedMIPSP8700.td

[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865 )

2025-01-22 10:37:01 -08:00

RISCVSchedRocket.td

[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329 )

2024-12-17 21:32:50 -08:00

RISCVSchedSiFive7.td

[llvm][NFC] Fix typos: replace “avaliable” with “available” across various files (#114524 )

2024-11-01 13:25:04 +00:00

RISCVSchedSiFiveP400.td

[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (#122007 )

2025-01-07 15:01:05 -08:00

RISCVSchedSiFiveP600.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893 )

2024-11-21 10:59:46 -08:00

RISCVSchedSyntacoreSCR1.td

[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC

2025-01-21 18:00:52 -08:00

RISCVSchedSyntacoreSCR7.td

[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329 )

2024-12-17 21:32:50 -08:00

RISCVSchedSyntacoreSCR345.td

[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329 )

2024-12-17 21:32:50 -08:00

RISCVSchedTTAscalonD8.td

[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160 )

2024-12-20 15:30:17 -05:00

RISCVSchedule.td

[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh

2024-12-31 17:22:08 +08:00

RISCVScheduleV.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009 )

2024-10-28 09:37:54 -07:00

RISCVScheduleXSf.td

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RISCVScheduleZb.td

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RISCVScheduleZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317 )

2024-10-31 10:21:14 -07:00

RISCVSchedXiangShanNanHu.td

[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329 )

2024-12-17 21:32:50 -08:00

RISCVSelectionDAGInfo.cpp

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969 )

2024-12-21 05:29:51 +03:00

RISCVSelectionDAGInfo.h

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969 )

2024-12-21 05:29:51 +03:00

RISCVSubtarget.cpp

[RISCV] Add software pipeliner support (#117546 )

2024-12-19 13:00:08 +08:00

RISCVSubtarget.h

[RISCV] Add software pipeliner support (#117546 )

2024-12-19 13:00:08 +08:00

RISCVSystemOperands.td

[RISCV] Add Enum for CSR encodings. (#121674 )

2025-01-06 10:11:29 -08:00

RISCVTargetMachine.cpp

[RISCV] Add software pipeliner support (#117546 )

2024-12-19 13:00:08 +08:00

RISCVTargetMachine.h

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968 )

2024-12-16 15:13:46 +03:00

RISCVTargetObjectFile.cpp

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

[RISCV][CostModel] Add cost for fabs/fsqrt of type bf16/f16 (#118608 )

2025-01-10 17:22:51 +08:00

RISCVTargetTransformInfo.h

[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533 )

2024-12-31 10:56:28 +08:00

RISCVVectorMaskDAGMutation.cpp

[RISCV] Set a barrier between mask producer and user of V0 (#114012 )

2024-11-29 13:25:53 +08:00

RISCVVectorPeephole.cpp

[RISCV] Fix masked->unmasked peephole handling masked pseudos with no passthru (#122253 )

2025-01-09 19:54:37 +08:00

RISCVVLOptimizer.cpp

[RISCV][VLOPT] support fp sign injection instructions (#124195 )

2025-01-23 16:50:35 -05:00

RISCVZacasABIFix.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00