1e8e662174
These are identified by misc-include-cleaner. I've filtered out those that break builds. Also, I'm staying away from llvm-config.h, config.h, and Compiler.h, which likely cause platform- or compiler-specific build failures.
112 lines
3.4 KiB
C++
112 lines
3.4 KiB
C++
//===-- AMDGPUReserveWWMRegs.cpp - Add WWM Regs to reserved regs list -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass should be invoked at the end of wwm-regalloc pipeline.
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/// It identifies the WWM regs allocated during this pipeline and add
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/// them to the list of reserved registers so that they won't be available for
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/// per-thread VGPR allocation in the subsequent regalloc pipeline.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUReserveWWMRegs.h"
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#include "AMDGPU.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-reserve-wwm-regs"
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namespace {
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class AMDGPUReserveWWMRegsLegacy : public MachineFunctionPass {
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public:
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static char ID;
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AMDGPUReserveWWMRegsLegacy() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "AMDGPU Reserve WWM Registers";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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class AMDGPUReserveWWMRegs {
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public:
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bool run(MachineFunction &MF);
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(AMDGPUReserveWWMRegsLegacy, DEBUG_TYPE,
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"AMDGPU Reserve WWM Registers", false, false)
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char AMDGPUReserveWWMRegsLegacy::ID = 0;
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char &llvm::AMDGPUReserveWWMRegsLegacyID = AMDGPUReserveWWMRegsLegacy::ID;
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bool AMDGPUReserveWWMRegsLegacy::runOnMachineFunction(MachineFunction &MF) {
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return AMDGPUReserveWWMRegs().run(MF);
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}
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PreservedAnalyses
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AMDGPUReserveWWMRegsPass::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &) {
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AMDGPUReserveWWMRegs().run(MF);
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// TODO: This should abandon RegisterClassInfo once it is turned into an
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// analysis.
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return PreservedAnalyses::all();
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}
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bool AMDGPUReserveWWMRegs::run(MachineFunction &MF) {
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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unsigned Opc = MI.getOpcode();
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if (Opc != AMDGPU::SI_SPILL_S32_TO_VGPR &&
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Opc != AMDGPU::SI_RESTORE_S32_FROM_VGPR)
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continue;
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Register Reg = Opc == AMDGPU::SI_SPILL_S32_TO_VGPR
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? MI.getOperand(0).getReg()
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: MI.getOperand(1).getReg();
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assert(Reg.isPhysical() &&
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"All WWM registers should have been allocated by now.");
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MFI->reserveWWMRegister(Reg);
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Changed |= true;
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}
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}
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// The renamable flag can't be set for reserved registers. Reset the flag for
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// MOs involving wwm-regs as they will be reserved during vgpr-regalloc
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// pipeline.
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (Register Reg : MFI->getWWMReservedRegs()) {
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for (MachineOperand &MO : MRI.reg_operands(Reg))
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MO.setIsRenamable(false);
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}
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// Now clear the NonWWMRegMask earlier set during wwm-regalloc.
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MFI->clearNonWWMRegAllocMask();
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return Changed;
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}
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