c1fabd681f
From GFX10 onwards it is possible to employ benevolent scheduling of waves. This patch unconditionally enables, for the `amdhsa` OS, the bit which controls that capability, as it is beneficial for algorithms that rely on more complex concurrent coordination and it is generally performance neutral otherwise.
124 lines
3.9 KiB
C++
124 lines
3.9 KiB
C++
//===--- SIProgramInfo.h ----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Defines struct to track resource usage and hardware flags for kernels and
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/// entry functions.
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///
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Support/Compiler.h"
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#include <cstdint>
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#include <optional>
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namespace llvm {
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class GCNSubtarget;
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class MCContext;
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class MCExpr;
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class MachineFunction;
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/// Track resource usage for kernels / entry functions.
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struct LLVM_EXTERNAL_VISIBILITY SIProgramInfo {
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std::optional<uint64_t> CodeSizeInBytes;
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// Fields set in PGM_RSRC1 pm4 packet.
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const MCExpr *VGPRBlocks = nullptr;
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const MCExpr *SGPRBlocks = nullptr;
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uint32_t Priority = 0;
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uint32_t FloatMode = 0;
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uint32_t Priv = 0;
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uint32_t DX10Clamp = 0;
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uint32_t DebugMode = 0;
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uint32_t IEEEMode = 0;
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uint32_t WgpMode = 0; // GFX10+
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uint32_t MemOrdered = 0; // GFX10+
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uint32_t FwdProgress = 0; // GFX10+
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uint32_t RrWgMode = 0; // GFX12+
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const MCExpr *ScratchSize = nullptr;
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// State used to calculate fields set in PGM_RSRC2 pm4 packet.
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uint32_t LDSBlocks = 0;
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const MCExpr *ScratchBlocks = nullptr;
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// Fields set in PGM_RSRC2 pm4 packet
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const MCExpr *ScratchEnable = nullptr;
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uint32_t UserSGPR = 0;
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uint32_t TrapHandlerEnable = 0;
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uint32_t TGIdXEnable = 0;
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uint32_t TGIdYEnable = 0;
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uint32_t TGIdZEnable = 0;
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uint32_t TGSizeEnable = 0;
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uint32_t TIdIGCompCount = 0;
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uint32_t EXCPEnMSB = 0;
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uint32_t LdsSize = 0;
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uint32_t EXCPEnable = 0;
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const MCExpr *ComputePGMRSrc3 = nullptr;
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const MCExpr *NumVGPR = nullptr;
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const MCExpr *NumArchVGPR = nullptr;
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const MCExpr *NumAccVGPR = nullptr;
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const MCExpr *AccumOffset = nullptr;
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uint32_t TgSplit = 0;
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const MCExpr *NumSGPR = nullptr;
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unsigned SGPRSpill = 0;
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unsigned VGPRSpill = 0;
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uint32_t LDSSize = 0;
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const MCExpr *FlatUsed = nullptr;
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// Number of SGPRs that meets number of waves per execution unit request.
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const MCExpr *NumSGPRsForWavesPerEU = nullptr;
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// Number of VGPRs that meets number of waves per execution unit request.
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const MCExpr *NumVGPRsForWavesPerEU = nullptr;
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// Final occupancy.
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const MCExpr *Occupancy = nullptr;
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// Whether there is recursion, dynamic allocas, indirect calls or some other
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// reason there may be statically unknown stack usage.
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const MCExpr *DynamicCallStack = nullptr;
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// Bonus information for debugging.
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const MCExpr *VCCUsed = nullptr;
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SIProgramInfo() = default;
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// The constructor sets the values for each member as shown in the struct.
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// However, setting the MCExpr members to their zero value equivalent
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// happens in reset together with (duplicated) value re-set for the
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// non-MCExpr members.
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void reset(const MachineFunction &MF);
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// Get function code size and cache the value.
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// If \p IsLowerBound is set it returns a minimal code size which is safe
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// to address.
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uint64_t getFunctionCodeSize(const MachineFunction &MF,
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bool IsLowerBound = false);
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/// Compute the value of the ComputePGMRsrc1 register.
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const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST,
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MCContext &Ctx) const;
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const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST,
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MCContext &Ctx) const;
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/// Compute the value of the ComputePGMRsrc2 register.
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const MCExpr *getComputePGMRSrc2(MCContext &Ctx) const;
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const MCExpr *getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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