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llvm-project/llvm/test/Transforms/SLPVectorizer
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Jinsong Ji 642bde76c3
[SLP] Fix infinite loop in ordered reduction worklist processing (#188342) 
The ordered reduction support introduced in 94e366ef2060 can cause an
infinite loop when processing complex reduction chains. The worklist
algorithm re-adds instructions from PossibleOrderedReductionOps when
switching to ordered mode, but doesn't track which instructions have
already been processed. This allows instructions to be re-added and
processed multiple times, creating cycles.

Add a Visited set to track processed instructions and skip any that
have already been handled, preventing the infinite loop.
2026-03-24 21:19:53 +00:00
..
AArch64
[SLP][NFC]Add a test with the non-profitable alternate vectorization, not throttled
2026-03-24 07:50:44 -07:00
AMDGPU
[AMDGPU] Add f32 cost model for exp/exp2/exp10 intrinsics (#185369)
2026-03-10 11:08:39 -05:00
ARM
[SLP]Check the MainOp matches the requirements for the instructions
2025-01-28 06:00:52 -08:00
NVPTX
[SLP]Exclude non-profitable subtrees.
2025-12-30 09:32:05 -08:00
PowerPC
[SLP]Disable modeling disjoint reduction or as bitcast for big endian
2026-02-03 06:16:25 -08:00
RISCV
[SLP]Do not consider copyable node with SplitVectorize parent
2026-03-21 06:56:59 -07:00
SystemZ
[SLP] Loop aware cost model/tree building
2026-03-18 17:54:01 -04:00
VE
…
WebAssembly
[WebAssembly] Add initial shuffle cost capabilities (#187596)
2026-03-23 09:28:37 -07:00
X86
[SLP]Use reduction root explicitly from reduction analysis to avoid non-determinism
2026-03-23 09:46:33 -07:00
XCore
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abs-overflow-incorrect-minbws.ll
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addsub.ll
[SLP]Reduce number of alternate instruction, where possible
2025-03-12 08:18:51 -07:00
alt-cmp-vectorize.ll
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alternate-cmp-swapped-pred-parent.ll
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alternate-non-profitable.ll
[SLP]Prefer copyable over alternate
2026-03-20 11:59:59 -04:00
alternate-opcode-sindle-bv.ll
[AArch64,TTI] Remove RealUse check for vector insert/extract costs. (#146526)
2025-07-15 15:19:27 +01:00
arith-div-undef.ll
…
bbi-106161.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
big-number-reduced-values.ll
[SLP]Do not overflow number of the reduced values
2026-02-15 11:02:32 -08:00
bool-logical-op-reduction-with-poison.ll
[SLP]Enable Shl as a base opcode in copyables (#156766)
2025-10-06 07:07:37 -04:00
boolean-op-with-poisons.ll
[SLP]FIx order of bool logical ops, if the right op is used in the first reduction operarion
2025-12-28 11:52:44 -08:00
buildvector-insert-mask-size.ll
…
buildvector-nodes-dependency.ll
[SLP] Initial support for ordered reductions
2026-03-20 13:45:14 -04:00
call-arg-reduced-by-minbitwidth.ll
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catchswitch.ll
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consecutive-access.ll
[SLP] Loop aware cost model/tree building
2026-03-18 17:54:01 -04:00
const-bool-logical-or-reduction.ll
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crash_exceed_scheduling.ll
[SLP]Enable float point math ops as copyables elements.
2025-12-26 11:55:58 -08:00
crash_extractelement_poison.ll
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diamond_broadcast.ll
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empty-struct.ll
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ext-after-phi-node.ll
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ext-int-reduced-not-operand.ll
[SLP]Remove Alternate early profitability checks in favor of throttling
2026-03-08 09:37:51 -04:00
extended-vectorized-gathered-inst.ll
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external-user-instruction-minbitwidth.ll
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extract_with_non_const_index.ll
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extract-many-users-buildvector.ll
[SLP]Prefer copyable over alternate
2026-03-20 11:59:59 -04:00
extract-vectorized-operand.ll
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extractelement-insertpoint.ll
[llvm][test] Fix REQUIRES in extractelement-insertpoint.ll
2025-07-03 13:14:42 +00:00
extractlements-gathered-first-node.ll
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extracts-with-undefs.ll
[SLP]Initial FMAD support (#149102)
2025-08-11 05:53:55 -07:00
fix-113880.ll
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freeze-signedness-missed.ll
[SLP] Loop aware cost model/tree building
2026-03-18 17:54:01 -04:00
full-overlap-non-schedulable.ll
[SLPVectorizer] Move X86 specific handling into X86TTIImpl. (#137830)
2025-04-30 17:11:27 +02:00
gather_extract_from_vectorbuild.ll
[SLP]Exclude non-profitable subtrees.
2025-12-30 09:32:05 -08:00
gathered-consecutive-loads-different-types.ll
[SLP]Initial support for copyable elements
2025-08-11 09:41:19 -04:00
gep-with-extractelement-many-users.ll
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insert-crash-index.ll
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insert-element-build-vector-const.ll
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insert-element-build-vector-inseltpoison.ll
[SLP]Fix patterns for compile time blow up with ordered reductions
2026-03-22 13:42:54 -07:00
insert-element-build-vector.ll
[SLP]Fix patterns for compile time blow up with ordered reductions
2026-03-22 13:42:54 -07:00
insert-element-multiple-uses.ll
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insert-shuffle.ll
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insertelement-across-zero.ll
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insertelement-postpone.ll
[SLP]Enable float point math ops as copyables elements.
2025-12-26 11:55:58 -08:00
insertelement-uses-vectorized-index.ll
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InstructionsState-is-invalid-2.ll
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int_sideeffect.ll
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int-bitcast-minbitwidth.ll
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is_fpclass.ll
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isCommutative.ll
[SLP] Fix isCommutative to check uses of the original instruction instead of the converted instruction. (#143094)
2025-06-17 22:03:14 +08:00
isOpcodeOrAlt.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
jumbled_store_crash.ll
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last-buildvector-node.ll
[SLP]Recalculate dependencies for the buildvector schedule node, if they have copyable node
2026-02-28 12:29:47 -08:00
limit.ll
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loads-with-large-distance.ll
[SLP] Fix a very long loads offset, being stored in DenseMap
2026-02-16 11:07:22 -08:00
logical-ops-poisonous-repeated.ll
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materialize-vector-of-consts.ll
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minbitwidth-multiuse-with-insertelement.ll
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minbitwidth-node-with-multi-users.ll
[SLP]Enable support for logical ops in copyables (#162945)
2025-10-13 08:01:32 -04:00
minbitwidth-user-not-min.ll
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multi-node-vectorized-insts.ll
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multi-uses-with-deps-in-first.ll
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non-power-of-2-bswap.ll
[SLP]Fix legality checks for bswap-based transformations
2026-03-16 11:56:24 -07:00
one-element-vector.ll
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operand-is-reduced-val.ll
[SLP]Prefer copyable over alternate
2026-03-20 11:59:59 -04:00
order-reduction-infinite-loop.ll
[SLP] Fix infinite loop in ordered reduction worklist processing (#188342)
2026-03-24 21:19:53 +00:00
orig-btiwidth-les-projected.ll
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partial-register-extract.ll
[SLP]Remove emission of vector_insert/vector_extract intrinsics
2025-07-11 15:26:45 -04:00
peek-through-shuffle.ll
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phi-not-ordered.ll
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phi-undef-input.ll
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postponed_gathers.ll
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pr31599-inseltpoison.ll
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pr31599.ll
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rdar128092379.ll
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reduced-gathered-vectorized.ll
[SLP] Loop aware cost model/tree building
2026-03-18 17:54:01 -04:00
reduction_loads.ll
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reduction-gather-non-scheduled-extracts.ll
[IR] Mark reduction intrinsics as nocreateundeforpoison (#184173)
2026-03-03 09:51:12 +01:00
reduction-min-select.ll
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reduction-modified-values.ll
[SLP]Prefer copyable over alternate
2026-03-20 11:59:59 -04:00
reduction-root-node-with-no-state-but-gathered-loads.ll
[SLP]Do not request the last instruction for first buildvector nodes with no state
2026-03-11 10:11:09 -07:00
reduction-whole-regs-loads.ll
[SLP]Remove emission of vector_insert/vector_extract intrinsics
2025-07-11 15:26:45 -04:00
reductions.ll
[LV] Create in-loop sub reductions (#147026)
2025-08-12 10:22:41 +01:00
reorder-clustered-node.ll
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reorder-node.ll
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reordered-top-scalars.ll
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reordering-single-phi.ll
[SLP]Model single unique value insert + shuffle as splat + select, where profitable
2025-04-22 11:30:29 -04:00
reschedule.ll
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resized-alt-shuffle-after-minbw.ll
[SLP]Prefer copyable over alternate
2026-03-20 11:59:59 -04:00
return.ll
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reudction-or-non-poisoned.ll
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reused-buildvector-matching-vectorized-node.ll
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reused-scalar-in-multi-node.ll
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revec-fix-109835.ll
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revec-insertelement.ll
[SLP]Remove emission of vector_insert/vector_extract intrinsics
2025-07-11 15:26:45 -04:00
revec-reduction-logical.ll
[SLP]Remove emission of vector_insert/vector_extract intrinsics
2025-07-11 15:26:45 -04:00
revec-shufflevector.ll
[SLP]Remove emission of vector_insert/vector_extract intrinsics
2025-07-11 15:26:45 -04:00
revec.ll
[SLP]Initial support for copyable elements
2025-08-11 09:41:19 -04:00
root-trunc-extract-reuse.ll
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same-scalar-in-same-phi-extract.ll
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same-scalars-reordered-in-reduction.ll
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scalarazied-result.ll
[AArch64] Add better fcmp costs for expanded predicates (#147940)
2025-08-04 13:42:57 +01:00
scalarization-overhead.ll
[SLP]Improved reduction cost/codegen
2025-02-14 11:03:33 -08:00
semanticly-same.ll
[SLP][NFC] Precommit tests for LShr-UDiv power of 2 transformations (#181925)
2026-02-17 15:07:51 -08:00
several_store_chains.ll
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shrink_after_reorder2.ll
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shuffle-mask-resized.ll
[SLP] Make getSameOpcode support interchangeable instructions. (#135797)
2025-04-16 00:08:59 +08:00
shuffle-multivector.ll
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shufflebuilder-bug.ll
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slp-deleted-inst.ll
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slp-hr-with-reuse.ll
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slp-max-phi-size.ll
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slp-max-reg-size.ll
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slp-non-pow-2-insertelement.ll
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slp-umax-rdx-matcher-crash.ll
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slp-variable-insertelement.ll
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splat-buildvector.ll
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stores-non-ordered.ll
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test_intermediate_dual_use.ll
[SLP]Do not swap RHS, if it is used in bool op, used as a second operand in a reduction
2025-12-28 13:33:17 -08:00
unknown-entries.ll
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vectorizable-functions-inseltpoison.ll
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vectorizable-functions.ll
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vectorize-reorder-alt-shuffle.ll
[SLP]Exclude non-profitable subtrees.
2025-12-30 09:32:05 -08:00
vectorize-reordered-list.ll
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zext-incoming-for-neg-icmp.ll
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