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llvm-project/llvm/test/CodeGen
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Eric Christopher cf23852587 [Target] As part of using inclusive language within the llvm project, 
migrate away from the use of blacklist and whitelist.

This change affects an internal llvm command line option.
2020-06-20 00:06:39 -07:00
..
AArch64
[AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.
2020-06-19 13:20:41 -07:00
AMDGPU
[AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
2020-06-20 12:10:47 +09:00
ARC
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ARM
[ARM][BFloat] Implement lowering of bf16 load/store intrinsics
2020-06-19 14:02:35 +00:00
AVR
[AVR] Fix miscompilation of zext + add
2020-06-18 16:51:37 +02:00
BPF
[BPF] fix a bug for BTF pointee type pruning
2020-06-17 15:13:46 -07:00
Generic
[LLParser] Delete temp CallInst when error occurs
2020-06-16 11:41:25 +08:00
Hexagon
Simplify MachineVerifier's block-successor verification.
2020-06-06 22:30:51 -04:00
Inputs
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Lanai
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Mips
[DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2))
2020-06-12 13:53:08 -04:00
MIR
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
MSP430
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NVPTX
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PowerPC
[PowerPC] Canonicalize shuffles to match more single-instruction masks on LE
2020-06-18 21:54:22 -05:00
RISCV
[RISCV64] Emit correct lib call for fp(float/double) to ui/si
2020-06-18 19:34:16 +05:30
SPARC
[SPARC] Lower fp16 ops to libcalls
2020-06-10 19:15:26 -07:00
SystemZ
[SystemZ] Bugfix in storeLoadCanUseBlockBinary().
2020-06-17 09:49:31 +02:00
Thumb
[ARM] Don't shrink STM if it would cause an unknown base register store
2020-04-22 14:50:42 +01:00
Thumb2
[ARM][MVE] tail-predication: renamed internal option.
2020-06-19 15:07:06 +01:00
VE
[VE] Support relocation information in MC layer
2020-06-15 11:24:53 +02:00
WebAssembly
[Target] As part of using inclusive language within the llvm project,
2020-06-20 00:06:39 -07:00
WinCFGuard
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WinEH
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X86
[X86][SSE] movmsk-cmp.ll - cleanup check prefixes and add SSE41 target tests
2020-06-19 15:24:59 +01:00
XCore
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