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llvm-project/llvm/test/CodeGen
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Petar Avramovic 66de26b1f9 GlobalISel: Fix matchEqualDefs for instructions with multiple defs 
Instructions that produceSameValue produce same values for operands with
same index. matchEqualDefs used to return true for any two values from
different instructions that produce same values. Fix this by checking if
values are defined by operands with the same index.

Differential Revision: https://reviews.llvm.org/D107362
2021-08-05 15:05:45 +02:00
..
AArch64
[GlobalISel] Combine shr(shl x, c1), c2 to G_SBFX/G_UBFX
2021-08-05 13:52:10 +02:00
AMDGPU
GlobalISel: Fix matchEqualDefs for instructions with multiple defs
2021-08-05 15:05:45 +02:00
ARC
…
ARM
[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert
2021-08-04 15:02:02 +01:00
AVR
[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'
2021-08-05 10:37:36 +08:00
BPF
BPF: avoid NE/EQ loop exit condition
2021-08-04 16:54:16 -07:00
Generic
[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX
2021-07-26 23:21:38 +00:00
Hexagon
[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs
2021-07-27 18:36:28 -05:00
Inputs
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Lanai
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M68k
[M68k][GloballSel] LegalizerInfo implementation
2021-07-15 13:00:43 -06:00
Mips
GlobalISel/AArch64: don't optimize away redundant branches at -O0
2021-07-29 16:04:22 -07:00
MIR
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MSP430
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NVPTX
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
PowerPC
Revert "Introduce intrinsic llvm.isnan"
2021-08-04 17:18:15 +07:00
RISCV
[CodeGen] Add -align-loops
2021-08-04 12:45:18 -07:00
SPARC
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SystemZ
[NFC][Codegen][SystemZ] Autogenerate checklines in int-cmp-47.ll
2021-08-04 01:47:39 +03:00
Thumb
[ARM] Regenerate Thumb PR35481.ll test. NFC
2021-07-31 16:21:23 +01:00
Thumb2
[RDA] Attempt to make RDA subreg aware
2021-08-04 14:21:32 +01:00
VE
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WebAssembly
[WebAssembly] Cleanup Emscripten SjLj tests
2021-08-04 21:16:08 -07:00
WinCFGuard
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WinEH
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X86
[CodeGen] Add -align-loops
2021-08-04 12:45:18 -07:00
XCore
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