16a385ba21
We already created a versioned `__tgt_kernel_arguments` struct but it
was only briefly used and its content was passed in isolation anyway.
This makes it hard to add more information in the future. With this
patch we fully embrace the struct as means to pass information from the
compiler to the plugin as part of a kernel launch.
The patch also extends and renames the struct, bumping the version
number to 2. Version 1 entries are auto-upgraded. This is in preparation
for "bare" kernel launches, per kernel dynamic shared memory, CUDA/HIP
lowering, etc.
The `__tgt_target_kernel_nowait` interface was deprecated as it was
unused. Once we actually implement support for something like that, we
can add an appropriate API.
Note: Only plugins with the `launch_kernel` interface are now supported.
That means that a new clang won't be able to use an old runtime.
An old clang can still use the new runtime since the libomptarget
interface did not change.
Differential Revision: https://reviews.llvm.org/D141232
1505 lines
106 KiB
C++
1505 lines
106 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// REQUIRES: powerpc-registered-target
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// REQUIRES: nvptx-registered-target
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK2
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -emit-pch -o %t
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -o - | FileCheck %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -o - | FileCheck %s --check-prefix=CHECK3
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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template <typename T>
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int foo(const T &t) {
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#pragma omp target parallel
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t();
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return 0;
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}
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struct S {
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int a = 15;
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int foo() {
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auto &&L = [&]() { return a; };
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#pragma omp target
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L();
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#pragma omp target parallel
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L();
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return a + ::foo(L);
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}
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} s;
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int main(int argc, char **argv) {
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int &b = argc;
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int &&c = 1;
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int *d = &argc;
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int a;
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auto &&L = [&]() { return argc + b + c + reinterpret_cast<long int>(d) + a; };
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#pragma omp target firstprivate(argc) map(to : a)
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L();
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#pragma omp target parallel
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L();
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return argc + s.foo();
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}
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#endif // HEADER
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// CHECK1-LABEL: define {{[^@]+}}@main
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// CHECK1-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[B:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[C:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[D:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[L:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[REF_TMP1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
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// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [11 x ptr], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [11 x ptr], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [11 x ptr], align 8
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// CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [11 x ptr], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [11 x ptr], align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [11 x ptr], align 8
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// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
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// CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
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// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
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// CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[B]], align 8
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// CHECK1-NEXT: store i32 1, ptr [[REF_TMP]], align 4
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// CHECK1-NEXT: store ptr [[REF_TMP]], ptr [[C]], align 8
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// CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[D]], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 0
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// CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP0]], align 8
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// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 1
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|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 8
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// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8
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// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 2
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|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C]], align 8
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|
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 8
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|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 3
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// CHECK1-NEXT: store ptr [[D]], ptr [[TMP5]], align 8
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// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP1]], i32 0, i32 4
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// CHECK1-NEXT: store ptr [[A]], ptr [[TMP6]], align 8
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// CHECK1-NEXT: store ptr [[REF_TMP1]], ptr [[L]], align 8
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|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[B]], align 8
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|
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP]], align 8
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|
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[C]], align 8
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|
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[_TMP2]], align 8
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// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[L]], align 8
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|
// CHECK1-NEXT: store ptr [[TMP9]], ptr [[_TMP3]], align 8
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|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
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|
// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARGC_CASTED]], align 4
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// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8
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// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 8
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|
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8
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|
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[D]], align 8
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|
// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP3]], align 8
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|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 0
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|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 0
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|
// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 1
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|
// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8
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|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 3
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|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 3
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|
// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8
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|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 4
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|
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP15]], i32 0, i32 4
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|
// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8
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|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
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|
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[TMP31]], align 8
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|
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
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|
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[TMP32]], align 8
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|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
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|
// CHECK1-NEXT: store ptr null, ptr [[TMP33]], align 8
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|
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
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|
// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP34]], align 8
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|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
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|
// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP35]], align 8
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|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
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|
// CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8
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|
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
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|
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP37]], align 8
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|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
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|
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP38]], align 8
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|
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
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|
// CHECK1-NEXT: store ptr null, ptr [[TMP39]], align 8
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|
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
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|
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP40]], align 8
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|
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
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|
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP41]], align 8
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|
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP42]], align 8
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP43]], align 8
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP44]], align 8
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP45]], align 8
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP46]], align 8
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP47]], align 8
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP48]], align 8
|
|
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP49]], align 8
|
|
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP50]], align 8
|
|
// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP51]], align 8
|
|
// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP52]], align 8
|
|
// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP53]], align 8
|
|
// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP54]], align 8
|
|
// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP55]], align 8
|
|
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP56]], align 8
|
|
// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP57]], align 8
|
|
// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP58]], align 8
|
|
// CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP59]], align 8
|
|
// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP60]], align 8
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP61]], align 8
|
|
// CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store ptr [[TMP30]], ptr [[TMP62]], align 8
|
|
// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 10
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP63]], align 8
|
|
// CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP66]], align 4
|
|
// CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 11, ptr [[TMP67]], align 4
|
|
// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP64]], ptr [[TMP68]], align 8
|
|
// CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP65]], ptr [[TMP69]], align 8
|
|
// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP70]], align 8
|
|
// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP71]], align 8
|
|
// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP72]], align 8
|
|
// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP73]], align 8
|
|
// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP74]], align 8
|
|
// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP75]], align 8
|
|
// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP76]], align 4
|
|
// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP77]], align 4
|
|
// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP78]], align 4
|
|
// CHECK1-NEXT: [[TMP79:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP80:%.*]] = icmp ne i32 [[TMP79]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP80]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41(i64 [[TMP11]], ptr [[TMP12]], ptr [[TMP13]], ptr [[TMP14]], ptr [[A]], ptr [[TMP15]]) #[[ATTR4:[0-9]+]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[TMP81:%.*]] = load ptr, ptr [[B]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP81]], ptr [[_TMP4]], align 8
|
|
// CHECK1-NEXT: [[TMP82:%.*]] = load ptr, ptr [[C]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP82]], ptr [[_TMP5]], align 8
|
|
// CHECK1-NEXT: [[TMP83:%.*]] = load ptr, ptr [[L]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP83]], ptr [[_TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP84:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK1-NEXT: [[TMP85:%.*]] = load ptr, ptr [[_TMP5]], align 8
|
|
// CHECK1-NEXT: [[TMP86:%.*]] = load ptr, ptr [[D]], align 8
|
|
// CHECK1-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[TMP89]], align 8
|
|
// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP93:%.*]] = load ptr, ptr [[TMP92]], align 8
|
|
// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP96:%.*]] = load ptr, ptr [[TMP95]], align 8
|
|
// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP99:%.*]] = load ptr, ptr [[TMP98]], align 8
|
|
// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP87]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP102:%.*]] = load ptr, ptr [[TMP101]], align 8
|
|
// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP103]], align 8
|
|
// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP104]], align 8
|
|
// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP105]], align 8
|
|
// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP84]], ptr [[TMP106]], align 8
|
|
// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP84]], ptr [[TMP107]], align 8
|
|
// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP108]], align 8
|
|
// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP85]], ptr [[TMP109]], align 8
|
|
// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP85]], ptr [[TMP110]], align 8
|
|
// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP111]], align 8
|
|
// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP86]], ptr [[TMP112]], align 8
|
|
// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP86]], ptr [[TMP113]], align 8
|
|
// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 3
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8
|
|
// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP115]], align 8
|
|
// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP116]], align 8
|
|
// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 4
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP117]], align 8
|
|
// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr [[TMP87]], ptr [[TMP118]], align 8
|
|
// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr [[TMP87]], ptr [[TMP119]], align 8
|
|
// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 5
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP120]], align 8
|
|
// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr [[TMP88]], ptr [[TMP121]], align 8
|
|
// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr [[TMP90]], ptr [[TMP122]], align 8
|
|
// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP123]], align 8
|
|
// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr [[TMP91]], ptr [[TMP124]], align 8
|
|
// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr [[TMP93]], ptr [[TMP125]], align 8
|
|
// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP126]], align 8
|
|
// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 8
|
|
// CHECK1-NEXT: store ptr [[TMP94]], ptr [[TMP127]], align 8
|
|
// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 8
|
|
// CHECK1-NEXT: store ptr [[TMP96]], ptr [[TMP128]], align 8
|
|
// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 8
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP129]], align 8
|
|
// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 9
|
|
// CHECK1-NEXT: store ptr [[TMP97]], ptr [[TMP130]], align 8
|
|
// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 9
|
|
// CHECK1-NEXT: store ptr [[TMP99]], ptr [[TMP131]], align 8
|
|
// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 9
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP132]], align 8
|
|
// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 10
|
|
// CHECK1-NEXT: store ptr [[TMP100]], ptr [[TMP133]], align 8
|
|
// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 10
|
|
// CHECK1-NEXT: store ptr [[TMP102]], ptr [[TMP134]], align 8
|
|
// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 10
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP135]], align 8
|
|
// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [11 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP138]], align 4
|
|
// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 11, ptr [[TMP139]], align 4
|
|
// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP136]], ptr [[TMP140]], align 8
|
|
// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 8
|
|
// CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP142]], align 8
|
|
// CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP143]], align 8
|
|
// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP144]], align 8
|
|
// CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP145]], align 8
|
|
// CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP146]], align 8
|
|
// CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP147]], align 8
|
|
// CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP148]], align 4
|
|
// CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP149]], align 4
|
|
// CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP150]], align 4
|
|
// CHECK1-NEXT: [[TMP151:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43.region_id, ptr [[KERNEL_ARGS10]])
|
|
// CHECK1-NEXT: [[TMP152:%.*]] = icmp ne i32 [[TMP151]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP152]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
|
|
// CHECK1: omp_offload.failed11:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43(ptr [[ARGC_ADDR]], ptr [[TMP84]], ptr [[TMP85]], ptr [[TMP86]], ptr [[A]], ptr [[TMP87]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT12]]
|
|
// CHECK1: omp_offload.cont12:
|
|
// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN1S3fooEv(ptr noundef nonnull align 4 dereferenceable(4) @s)
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP153]], [[CALL]]
|
|
// CHECK1-NEXT: ret i32 [[ADD]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
|
|
// CHECK1-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[B5:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C7:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP4]], i64 40, i1 false)
|
|
// CHECK1-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP6]], ptr [[B5]], align 4
|
|
// CHECK1-NEXT: store ptr [[B5]], ptr [[_TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[C7]], align 4
|
|
// CHECK1-NEXT: store ptr [[C7]], ptr [[_TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP9]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR5:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 6, ptr @.omp_outlined., ptr [[TMP0]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], ptr [[TMP3]], ptr [[TMP8]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[ARGC5:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[B6:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C8:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A10:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false)
|
|
// CHECK1-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARGC5]], align 4
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[B6]], align 4
|
|
// CHECK1-NEXT: store ptr [[B6]], ptr [[_TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP10]], ptr [[C8]], align 4
|
|
// CHECK1-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP12]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1S3fooEv
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR3:[0-9]+]] comdat align 2 {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8
|
|
// CHECK1-NEXT: store ptr [[REF_TMP]], ptr [[L]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP2]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP2]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP5]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP26]], align 4
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27(ptr [[THIS1]], ptr [[TMP2]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[L]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP31]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP32]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP32]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP35]], align 8
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP36]], align 8
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP32]], ptr [[TMP38]], align 8
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP32]], ptr [[TMP39]], align 8
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP40]], align 8
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP33]], ptr [[TMP41]], align 8
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP34]], ptr [[TMP42]], align 8
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP43]], align 8
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS6:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP46]], align 4
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 3, ptr [[TMP47]], align 4
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP44]], ptr [[TMP48]], align 8
|
|
// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP45]], ptr [[TMP49]], align 8
|
|
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.6, ptr [[TMP50]], align 8
|
|
// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.7, ptr [[TMP51]], align 8
|
|
// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP52]], align 8
|
|
// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP53]], align 8
|
|
// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP54]], align 8
|
|
// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP55]], align 8
|
|
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP56]], align 4
|
|
// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP57]], align 4
|
|
// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS6]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP58]], align 4
|
|
// CHECK1-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29.region_id, ptr [[KERNEL_ARGS6]])
|
|
// CHECK1-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
|
|
// CHECK1: omp_offload.failed7:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29(ptr [[THIS1]], ptr [[TMP32]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]]
|
|
// CHECK1: omp_offload.cont8:
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP62:%.*]] = load ptr, ptr [[L]], align 8
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooIZN1S3fooEvEUlvE_EiRKT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP62]])
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP61]], [[CALL]]
|
|
// CHECK1-NEXT: ret i32 [[ADD]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27
|
|
// CHECK1-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false)
|
|
// CHECK1-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
|
|
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR3]] comdat align 2 {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29
|
|
// CHECK1-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR5]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @.omp_outlined..5, ptr [[TMP0]], ptr [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false)
|
|
// CHECK1-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z3fooIZN1S3fooEvEUlvE_EiRKT_
|
|
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] comdat {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK1-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[TMP1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP4]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP5]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP12]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP13]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP22]], align 4
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP23]], align 4
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP24]], align 4
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18(ptr [[TMP1]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18
|
|
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR5]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..8, ptr [[TMP1]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR1]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[T1]], ptr align 8 [[TMP1]], i64 8, i1 false)
|
|
// CHECK1-NEXT: store ptr [[T1]], ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR6:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27
|
|
// CHECK2-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1:[0-9]+]], i8 1, i1 true)
|
|
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
|
|
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK2: user_code.entry:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP3]], i64 8, i1 false)
|
|
// CHECK2-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP4]], i32 0, i32 0
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP6]]) #[[ATTR7:[0-9]+]]
|
|
// CHECK2-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 1)
|
|
// CHECK2-NEXT: ret void
|
|
// CHECK2: worker.exit:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
|
|
// CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29
|
|
// CHECK2-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
|
|
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
|
|
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK2: user_code.entry:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store ptr [[TMP4]], ptr [[TMP6]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2)
|
|
// CHECK2-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
|
|
// CHECK2-NEXT: ret void
|
|
// CHECK2: worker.exit:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
|
|
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false)
|
|
// CHECK2-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP3]], i32 0, i32 0
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]]
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
|
|
// CHECK2-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK2-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[B5:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[C7:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 1, i1 true)
|
|
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
|
|
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK2: user_code.entry:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false)
|
|
// CHECK2-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP7]], ptr [[B5]], align 4
|
|
// CHECK2-NEXT: store ptr [[B5]], ptr [[_TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP9]], ptr [[C7]], align 4
|
|
// CHECK2-NEXT: store ptr [[C7]], ptr [[_TMP8]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP10]], i32 0, i32 0
|
|
// CHECK2-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP10]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP10]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP8]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP10]], i32 0, i32 3
|
|
// CHECK2-NEXT: store ptr [[D_ADDR]], ptr [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP10]], i32 0, i32 4
|
|
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP18]]) #[[ATTR7]]
|
|
// CHECK2-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 1)
|
|
// CHECK2-NEXT: ret void
|
|
// CHECK2: worker.exit:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43
|
|
// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [6 x ptr], align 8
|
|
// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
|
|
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1
|
|
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK2: user_code.entry:
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store ptr [[TMP7]], ptr [[TMP12]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
|
|
// CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
|
|
// CHECK2-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 5
|
|
// CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 6)
|
|
// CHECK2-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
|
|
// CHECK2-NEXT: ret void
|
|
// CHECK2: worker.exit:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
|
|
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK2-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[ARGC5:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[B6:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[C8:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[A10:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false)
|
|
// CHECK2-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP6]], ptr [[ARGC5]], align 4
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP8]], ptr [[B6]], align 4
|
|
// CHECK2-NEXT: store ptr [[B6]], ptr [[_TMP7]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP10]], ptr [[C8]], align 4
|
|
// CHECK2-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP12]], i32 0, i32 0
|
|
// CHECK2-NEXT: store ptr [[ARGC5]], ptr [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP12]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP12]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP9]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP12]], i32 0, i32 3
|
|
// CHECK2-NEXT: store ptr [[D_ADDR]], ptr [[TMP18]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP12]], i32 0, i32 4
|
|
// CHECK2-NEXT: store ptr [[A10]], ptr [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7]]
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18
|
|
// CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
|
|
// CHECK2-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
|
|
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
|
|
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK2: user_code.entry:
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8
|
|
// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
|
|
// CHECK2-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
|
|
// CHECK2-NEXT: ret void
|
|
// CHECK2: worker.exit:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
|
|
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK2-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
|
|
// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[T1]], ptr align 8 [[TMP1]], i64 8, i1 false)
|
|
// CHECK2-NEXT: store ptr [[T1]], ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) #[[ATTR7]]
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41
|
|
// CHECK3-SAME: (i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[B5:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[C7:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1:[0-9]+]], i8 1, i1 true)
|
|
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1
|
|
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK3: user_code.entry:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false)
|
|
// CHECK3-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP7]], ptr [[B5]], align 4
|
|
// CHECK3-NEXT: store ptr [[B5]], ptr [[_TMP6]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP9]], ptr [[C7]], align 4
|
|
// CHECK3-NEXT: store ptr [[C7]], ptr [[_TMP8]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP10]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP11]], align 8
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP10]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP10]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP8]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP10]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[D_ADDR]], ptr [[TMP16]], align 8
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP10]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP17]], align 8
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP18]]) #[[ATTR7:[0-9]+]]
|
|
// CHECK3-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 1)
|
|
// CHECK3-NEXT: ret void
|
|
// CHECK3: worker.exit:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l43
|
|
// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [6 x ptr], align 8
|
|
// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
|
|
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP5]], -1
|
|
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK3: user_code.entry:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
|
|
// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP11]], align 8
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
|
|
// CHECK3-NEXT: store ptr [[TMP7]], ptr [[TMP12]], align 8
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
|
|
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP13]], align 8
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
|
|
// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP14]], align 8
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
|
|
// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 5
|
|
// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP16]], align 8
|
|
// CHECK3-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 6)
|
|
// CHECK3-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
|
|
// CHECK3-NEXT: ret void
|
|
// CHECK3: worker.exit:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], ptr noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(40) [[L:%.*]]) #[[ATTR4:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L3:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
|
|
// CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[ARGC5:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B6:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[C8:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[A10:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L3]], ptr align 8 [[TMP5]], i64 40, i1 false)
|
|
// CHECK3-NEXT: store ptr [[L3]], ptr [[_TMP4]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP6]], ptr [[ARGC5]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[B6]], align 4
|
|
// CHECK3-NEXT: store ptr [[B6]], ptr [[_TMP7]], align 8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP10]], ptr [[C8]], align 4
|
|
// CHECK3-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP3]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP11]], ptr [[A10]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP12]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr [[ARGC5]], ptr [[TMP13]], align 8
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP12]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP12]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP9]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP12]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[D_ADDR]], ptr [[TMP18]], align 8
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[TMP12]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[A10]], ptr [[TMP19]], align 8
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP4]], align 8
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(40) [[TMP20]]) #[[ATTR7]]
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l27
|
|
// CHECK3-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
|
// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 1, i1 true)
|
|
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
|
|
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
|
|
// CHECK3: user_code.entry:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP3]], i64 8, i1 false)
|
|
// CHECK3-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP4]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP6]]) #[[ATTR7]]
|
|
// CHECK3-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 1)
|
|
// CHECK3-NEXT: ret void
|
|
// CHECK3: worker.exit:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZZN1S3fooEvENKUlvE_clEv
|
|
// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN1S3fooEv_l29
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// CHECK3-SAME: (ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR3]] {
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// CHECK3-NEXT: entry:
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// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
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// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
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// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
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// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
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// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
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// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP2]], -1
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// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
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// CHECK3: user_code.entry:
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// CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
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// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
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// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
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// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8
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// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
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// CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP6]], align 8
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// CHECK3-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__1, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2)
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// CHECK3-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
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// CHECK3-NEXT: ret void
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// CHECK3: worker.exit:
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// CHECK3-NEXT: ret void
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//
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//
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// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
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// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[L:%.*]]) #[[ATTR4]] {
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// CHECK3-NEXT: entry:
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// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[L1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
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// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
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// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
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// CHECK3-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
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// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
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// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L_ADDR]], align 8
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// CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8
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// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
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// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[L1]], ptr align 8 [[TMP2]], i64 8, i1 false)
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// CHECK3-NEXT: store ptr [[L1]], ptr [[_TMP2]], align 8
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// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
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// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[TMP3]], i32 0, i32 0
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// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8
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// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP2]], align 8
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// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR7]]
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// CHECK3-NEXT: ret void
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//
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//
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// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIZN1S3fooEvEUlvE_EiRKT__l18
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// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR3]] {
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// CHECK3-NEXT: entry:
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// CHECK3-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
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// CHECK3-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
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// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
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// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
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// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
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// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
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// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
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// CHECK3: user_code.entry:
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// CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
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// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
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// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
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// CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8
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// CHECK3-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
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// CHECK3-NEXT: call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
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// CHECK3-NEXT: ret void
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// CHECK3: worker.exit:
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// CHECK3-NEXT: ret void
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//
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//
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// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
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// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[T:%.*]]) #[[ATTR4]] {
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// CHECK3-NEXT: entry:
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// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[T1:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
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// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
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// CHECK3-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
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// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
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// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
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// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
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// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[T1]], ptr align 8 [[TMP1]], i64 8, i1 false)
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// CHECK3-NEXT: store ptr [[T1]], ptr [[_TMP2]], align 8
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// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8
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// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8
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// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZZN1S3fooEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(8) [[TMP3]]) #[[ATTR7]]
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// CHECK3-NEXT: ret void
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//
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