3b8c0b342e
RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
473 lines
18 KiB
C++
473 lines
18 KiB
C++
//===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to the RISCV assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVInstPrinter.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVTargetStreamer.h"
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#include "RISCV.h"
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#include "RISCVMachineFunctionInfo.h"
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#include "RISCVTargetMachine.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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STATISTIC(RISCVNumInstrsCompressed,
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"Number of RISC-V Compressed instructions emitted");
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namespace {
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class RISCVAsmPrinter : public AsmPrinter {
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const RISCVSubtarget *STI;
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public:
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explicit RISCVAsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)) {}
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StringRef getPassName() const override { return "RISCV Assembly Printer"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void emitInstruction(const MachineInstr *MI) override;
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &OS) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &OS) override;
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void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
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bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
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std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
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void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
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void EmitHwasanMemaccessSymbols(Module &M);
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// Wrapper needed for tblgenned pseudo lowering.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
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return lowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
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}
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void emitStartOfAsmFile(Module &M) override;
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void emitEndOfAsmFile(Module &M) override;
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void emitFunctionEntryLabel() override;
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private:
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void emitAttributes();
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};
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}
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void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
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MCInst CInst;
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bool Res = RISCVRVC::compress(CInst, Inst, *STI);
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if (Res)
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++RISCVNumInstrsCompressed;
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AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
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}
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// Simple pseudo-instructions have their lowering (with expansion to real
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// instructions) auto-generated.
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#include "RISCVGenMCPseudoLowering.inc"
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void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
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RISCV_MC::verifyInstructionPredicates(MI->getOpcode(),
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getSubtargetInfo().getFeatureBits());
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(*OutStreamer, MI))
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return;
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switch (MI->getOpcode()) {
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case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
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LowerHWASAN_CHECK_MEMACCESS(*MI);
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return;
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case RISCV::PseudoRVVInitUndefM1:
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case RISCV::PseudoRVVInitUndefM2:
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case RISCV::PseudoRVVInitUndefM4:
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case RISCV::PseudoRVVInitUndefM8:
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return;
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}
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MCInst TmpInst;
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if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
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EmitToStreamer(*OutStreamer, TmpInst);
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}
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bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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const char *ExtraCode, raw_ostream &OS) {
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// First try the generic code, which knows about modifiers like 'c' and 'n'.
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if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
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return false;
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0)
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return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default:
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return true; // Unknown modifier.
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case 'z': // Print zero register if zero, regular printing otherwise.
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if (MO.isImm() && MO.getImm() == 0) {
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OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
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return false;
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}
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break;
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case 'i': // Literal 'i' if operand is not a register.
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if (!MO.isReg())
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OS << 'i';
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return false;
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}
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}
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switch (MO.getType()) {
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case MachineOperand::MO_Immediate:
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OS << MO.getImm();
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return false;
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case MachineOperand::MO_Register:
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OS << RISCVInstPrinter::getRegisterName(MO.getReg());
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return false;
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case MachineOperand::MO_GlobalAddress:
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PrintSymbolOperand(MO, OS);
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return false;
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case MachineOperand::MO_BlockAddress: {
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MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
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Sym->print(OS, MAI);
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return false;
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}
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default:
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break;
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}
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return true;
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}
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bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo,
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const char *ExtraCode,
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raw_ostream &OS) {
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if (!ExtraCode) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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// For now, we only support register memory operands in registers and
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// assume there is no addend
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if (!MO.isReg())
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return true;
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OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
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return false;
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}
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return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
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}
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bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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STI = &MF.getSubtarget<RISCVSubtarget>();
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SetupMachineFunction(MF);
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emitFunctionBody();
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return false;
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}
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void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
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RISCVTargetStreamer &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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if (const MDString *ModuleTargetABI =
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dyn_cast_or_null<MDString>(M.getModuleFlag("target-abi")))
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RTS.setTargetABI(RISCVABI::getTargetABI(ModuleTargetABI->getString()));
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if (TM.getTargetTriple().isOSBinFormatELF())
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emitAttributes();
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}
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void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
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RISCVTargetStreamer &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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if (TM.getTargetTriple().isOSBinFormatELF())
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RTS.finishAttributeSection();
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EmitHwasanMemaccessSymbols(M);
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}
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void RISCVAsmPrinter::emitAttributes() {
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RISCVTargetStreamer &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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// Use MCSubtargetInfo from TargetMachine. Individual functions may have
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// attributes that differ from other functions in the module and we have no
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// way to know which function is correct.
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RTS.emitTargetAttributes(*TM.getMCSubtargetInfo());
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}
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void RISCVAsmPrinter::emitFunctionEntryLabel() {
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const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
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if (RMFI->isVectorCall()) {
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auto &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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RTS.emitDirectiveVariantCC(*CurrentFnSym);
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}
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return AsmPrinter::emitFunctionEntryLabel();
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}
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// Force static initialization.
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
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RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
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RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
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}
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void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
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Register Reg = MI.getOperand(0).getReg();
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uint32_t AccessInfo = MI.getOperand(1).getImm();
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MCSymbol *&Sym =
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HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
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if (!Sym) {
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// FIXME: Make this work on non-ELF.
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if (!TM.getTargetTriple().isOSBinFormatELF())
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report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
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std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" +
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utostr(AccessInfo) + "_short";
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Sym = OutContext.getOrCreateSymbol(SymName);
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}
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auto Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, OutContext);
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auto Expr = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL, OutContext);
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EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));
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}
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void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
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if (HwasanMemaccessSymbols.empty())
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return;
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assert(TM.getTargetTriple().isOSBinFormatELF());
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// Use MCSubtargetInfo from TargetMachine. Individual functions may have
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// attributes that differ from other functions in the module and we have no
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// way to know which function is correct.
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const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
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MCSymbol *HwasanTagMismatchV2Sym =
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OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2");
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// Annotate symbol as one having incompatible calling convention, so
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// run-time linkers can instead eagerly bind this function.
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auto &RTS =
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static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
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RTS.emitDirectiveVariantCC(*HwasanTagMismatchV2Sym);
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const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
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MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
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auto Expr = RISCVMCExpr::create(HwasanTagMismatchV2Ref,
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RISCVMCExpr::VK_RISCV_CALL, OutContext);
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for (auto &P : HwasanMemaccessSymbols) {
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unsigned Reg = std::get<0>(P.first);
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uint32_t AccessInfo = std::get<1>(P.first);
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MCSymbol *Sym = P.second;
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unsigned Size =
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1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
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OutStreamer->switchSection(OutContext.getELFSection(
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".text.hot", ELF::SHT_PROGBITS,
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ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(),
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/*IsComdat=*/true));
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OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
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OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
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OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
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OutStreamer->emitLabel(Sym);
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// Extract shadow offset from ptr
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8),
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MCSTI);
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI)
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.addReg(RISCV::X6)
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.addReg(RISCV::X6)
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.addImm(12),
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MCSTI);
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// load shadow tag in X6, X5 contains shadow base
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADD)
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.addReg(RISCV::X6)
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.addReg(RISCV::X5)
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.addReg(RISCV::X6),
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MCSTI);
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
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MCSTI);
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// Extract tag from X5 and compare it with loaded tag from shadow
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56),
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MCSTI);
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MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
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// X7 contains tag from memory, while X6 contains tag from the pointer
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::BNE)
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.addReg(RISCV::X7)
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.addReg(RISCV::X6)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
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OutContext)),
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MCSTI);
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MCSymbol *ReturnSym = OutContext.createTempSymbol();
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OutStreamer->emitLabel(ReturnSym);
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR)
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.addReg(RISCV::X0)
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.addReg(RISCV::X1)
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.addImm(0),
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MCSTI);
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OutStreamer->emitLabel(HandleMismatchOrPartialSym);
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
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.addReg(RISCV::X28)
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.addReg(RISCV::X0)
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.addImm(16),
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MCSTI);
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MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::BGEU)
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.addReg(RISCV::X6)
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.addReg(RISCV::X28)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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MCSTI);
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),
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MCSTI);
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if (Size != 1)
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
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.addReg(RISCV::X28)
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.addReg(RISCV::X28)
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.addImm(Size - 1),
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MCSTI);
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::BGE)
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.addReg(RISCV::X28)
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.addReg(RISCV::X6)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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MCSTI);
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),
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MCSTI);
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
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MCSTI);
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OutStreamer->emitInstruction(
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MCInstBuilder(RISCV::BEQ)
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.addReg(RISCV::X6)
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.addReg(RISCV::X7)
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.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
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MCSTI);
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OutStreamer->emitLabel(HandleMismatchSym);
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// | Previous stack frames... |
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// +=================================+ <-- [SP + 256]
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// | ... |
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// | |
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// | Stack frame space for x12 - x31.|
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// | |
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// | ... |
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// +---------------------------------+ <-- [SP + 96]
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// | Saved x11(arg1), as |
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// | __hwasan_check_* clobbers it. |
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// +---------------------------------+ <-- [SP + 88]
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// | Saved x10(arg0), as |
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// | __hwasan_check_* clobbers it. |
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// +---------------------------------+ <-- [SP + 80]
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// | |
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// | Stack frame space for x9. |
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// +---------------------------------+ <-- [SP + 72]
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// | |
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// | Saved x8(fp), as |
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// | __hwasan_check_* clobbers it. |
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// +---------------------------------+ <-- [SP + 64]
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// | ... |
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// | |
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// | Stack frame space for x2 - x7. |
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// | |
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// | ... |
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// +---------------------------------+ <-- [SP + 16]
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// | Return address (x1) for caller |
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// | of __hwasan_check_*. |
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// +---------------------------------+ <-- [SP + 8]
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// | Reserved place for x0, possibly |
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// | junk, since we don't save it. |
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// +---------------------------------+ <-- [x2 / SP]
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// Adjust sp
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
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.addReg(RISCV::X2)
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.addReg(RISCV::X2)
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.addImm(-256),
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MCSTI);
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// store x10(arg0) by new sp
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
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.addReg(RISCV::X10)
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.addReg(RISCV::X2)
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.addImm(8 * 10),
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MCSTI);
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// store x11(arg1) by new sp
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OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
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.addReg(RISCV::X11)
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.addReg(RISCV::X2)
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.addImm(8 * 11),
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MCSTI);
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// store x8(fp) by new sp
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OutStreamer->emitInstruction(
|
|
MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 *
|
|
8),
|
|
MCSTI);
|
|
// store x1(ra) by new sp
|
|
OutStreamer->emitInstruction(
|
|
MCInstBuilder(RISCV::SD).addReg(RISCV::X1).addReg(RISCV::X2).addImm(1 *
|
|
8),
|
|
MCSTI);
|
|
if (Reg != RISCV::X10)
|
|
OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
|
|
.addReg(RISCV::X10)
|
|
.addReg(Reg)
|
|
.addImm(0),
|
|
MCSTI);
|
|
OutStreamer->emitInstruction(
|
|
MCInstBuilder(RISCV::ADDI)
|
|
.addReg(RISCV::X11)
|
|
.addReg(RISCV::X0)
|
|
.addImm(AccessInfo & HWASanAccessInfo::RuntimeMask),
|
|
MCSTI);
|
|
|
|
OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
|
|
MCSTI);
|
|
}
|
|
}
|