33 lines
1.7 KiB
LLVM
33 lines
1.7 KiB
LLVM
; RUN: opt -mtriple amdgcn-amdhsa -mcpu=gfx90a -passes=legacy-divergence-analysis < %s -S 2>&1 | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.readfirstlane(i32)
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; OPT-LABEL: define amdgpu_kernel void @readfirstlane_uniform(
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; OPT-NEXT: %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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; OPT-NEXT: %scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid)
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; OPT-NEXT: %idx = zext i32 %scalar to i64
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; OPT-NEXT: %gep0 = getelementptr inbounds float, ptr addrspace(1) %0, i64 %idx
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; OPT-NEXT: %val = load float, ptr addrspace(1) %gep0, align 4
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; OPT-NEXT: %gep1 = getelementptr inbounds float, ptr addrspace(1) %1, i64 10
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; OPT-NEXT: store float %val, ptr addrspace(1) %gep1, align 4
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; OPT-NEXT: ret void
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;
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; GCN-LABEL: readfirstlane_uniform
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; GCN: s_load_dwordx4 s[[[IN_ADDR:[0-9]+]]:3], s[4:5], 0x0
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; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0
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; GCN: s_add_u32 s[[LOAD_ADDR:[0-9]+]], s[[IN_ADDR]], s[[SCALAR]]
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; GCN: s_load_dword s{{[0-9]+}}, s[[[LOAD_ADDR]]
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define amdgpu_kernel void @readfirstlane_uniform(ptr addrspace(1) noalias nocapture readonly, ptr addrspace(1) noalias nocapture readonly) {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid)
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%idx = zext i32 %scalar to i64
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%gep0 = getelementptr inbounds float, ptr addrspace(1) %0, i64 %idx
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%val = load float, ptr addrspace(1) %gep0, align 4
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%gep1 = getelementptr inbounds float, ptr addrspace(1) %1, i64 10
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store float %val, ptr addrspace(1) %gep1, align 4
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ret void
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}
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