10b7cd660c
The XTHeadBb extension hab both signed and unsigned bitfield extraction instructions (TH.EXT and TH.EXTU, respectively) which have previously only been supported for sign extension on byte, halfword, and word-boundaries. This adds the infrastructure to use TH.EXT and TH.EXTU for arbitrary bitfield extraction. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D144229
135 lines
4.7 KiB
LLVM
135 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32ZBB
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32XTHEADBB
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32XTHEADMAC
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32XTHEAD
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+zbb -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBB
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64XTHEADMAC
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64XTHEADBB
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+xtheadbb -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64XTHEAD
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define i32 @f(i32 %A, i32 %B, i32 %C) {
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; RV32I-LABEL: f:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: mul a0, a1, a0
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; RV32I-NEXT: slli a1, a0, 26
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; RV32I-NEXT: srli a1, a1, 28
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 25
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; RV32I-NEXT: mul a0, a1, a0
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: f:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: mul a0, a1, a0
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; RV32ZBB-NEXT: slli a1, a0, 26
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; RV32ZBB-NEXT: srli a1, a1, 28
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; RV32ZBB-NEXT: slli a0, a0, 20
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; RV32ZBB-NEXT: srli a0, a0, 25
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; RV32ZBB-NEXT: mul a0, a1, a0
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; RV32ZBB-NEXT: add a0, a0, a2
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; RV32ZBB-NEXT: ret
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;
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; RV32XTHEADBB-LABEL: f:
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; RV32XTHEADBB: # %bb.0: # %entry
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; RV32XTHEADBB-NEXT: mul a0, a1, a0
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; RV32XTHEADBB-NEXT: th.extu a1, a0, 5, 2
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; RV32XTHEADBB-NEXT: th.extu a0, a0, 11, 5
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; RV32XTHEADBB-NEXT: mul a0, a1, a0
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; RV32XTHEADBB-NEXT: add a0, a0, a2
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; RV32XTHEADBB-NEXT: ret
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;
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; RV32XTHEADMAC-LABEL: f:
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; RV32XTHEADMAC: # %bb.0: # %entry
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; RV32XTHEADMAC-NEXT: mul a0, a1, a0
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; RV32XTHEADMAC-NEXT: slli a1, a0, 26
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; RV32XTHEADMAC-NEXT: srli a1, a1, 28
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; RV32XTHEADMAC-NEXT: slli a0, a0, 20
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; RV32XTHEADMAC-NEXT: srli a0, a0, 25
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; RV32XTHEADMAC-NEXT: th.mulah a2, a1, a0
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; RV32XTHEADMAC-NEXT: mv a0, a2
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; RV32XTHEADMAC-NEXT: ret
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;
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; RV32XTHEAD-LABEL: f:
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; RV32XTHEAD: # %bb.0: # %entry
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; RV32XTHEAD-NEXT: mul a0, a1, a0
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; RV32XTHEAD-NEXT: th.extu a1, a0, 5, 2
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; RV32XTHEAD-NEXT: th.extu a0, a0, 11, 5
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; RV32XTHEAD-NEXT: th.mulah a2, a1, a0
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; RV32XTHEAD-NEXT: mv a0, a2
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; RV32XTHEAD-NEXT: ret
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;
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; RV64I-LABEL: f:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: mulw a0, a1, a0
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; RV64I-NEXT: slli a1, a0, 58
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; RV64I-NEXT: srli a1, a1, 60
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 57
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; RV64I-NEXT: mulw a0, a1, a0
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; RV64I-NEXT: addw a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: f:
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; RV64ZBB: # %bb.0: # %entry
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; RV64ZBB-NEXT: mulw a0, a1, a0
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; RV64ZBB-NEXT: slli a1, a0, 58
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; RV64ZBB-NEXT: srli a1, a1, 60
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; RV64ZBB-NEXT: slli a0, a0, 52
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; RV64ZBB-NEXT: srli a0, a0, 57
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; RV64ZBB-NEXT: mulw a0, a1, a0
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; RV64ZBB-NEXT: addw a0, a0, a2
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; RV64ZBB-NEXT: ret
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;
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; RV64XTHEADMAC-LABEL: f:
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; RV64XTHEADMAC: # %bb.0: # %entry
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; RV64XTHEADMAC-NEXT: mulw a0, a1, a0
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; RV64XTHEADMAC-NEXT: slli a1, a0, 58
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; RV64XTHEADMAC-NEXT: srli a1, a1, 60
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; RV64XTHEADMAC-NEXT: slli a0, a0, 52
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; RV64XTHEADMAC-NEXT: srli a0, a0, 57
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; RV64XTHEADMAC-NEXT: th.mulah a2, a1, a0
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; RV64XTHEADMAC-NEXT: mv a0, a2
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; RV64XTHEADMAC-NEXT: ret
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;
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; RV64XTHEADBB-LABEL: f:
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; RV64XTHEADBB: # %bb.0: # %entry
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; RV64XTHEADBB-NEXT: mul a0, a1, a0
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; RV64XTHEADBB-NEXT: th.extu a1, a0, 5, 2
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; RV64XTHEADBB-NEXT: th.extu a0, a0, 11, 5
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; RV64XTHEADBB-NEXT: mulw a0, a1, a0
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; RV64XTHEADBB-NEXT: addw a0, a0, a2
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; RV64XTHEADBB-NEXT: ret
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;
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; RV64XTHEAD-LABEL: f:
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; RV64XTHEAD: # %bb.0: # %entry
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; RV64XTHEAD-NEXT: mul a0, a1, a0
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; RV64XTHEAD-NEXT: th.extu a1, a0, 5, 2
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; RV64XTHEAD-NEXT: th.extu a0, a0, 11, 5
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; RV64XTHEAD-NEXT: th.mulah a2, a1, a0
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; RV64XTHEAD-NEXT: mv a0, a2
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; RV64XTHEAD-NEXT: ret
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entry:
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%mul = mul nsw i32 %B, %A
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%0 = lshr i32 %mul, 2
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%and = and i32 %0, 15
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%1 = lshr i32 %mul, 5
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%and2 = and i32 %1, 127
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%mul3 = mul nuw nsw i32 %and, %and2
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%add = add i32 %mul3, %C
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ret i32 %add
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}
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