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llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Piyou Chen 365f840398 [RISCV] Enable subregister liveness by default 
This commit enable the subregister liveness by default in RISC-V.

It was previously disabled in https://reviews.llvm.org/D129646 after a previous attempt to enabled it https://reviews.llvm.org/D128016.

We believe that https://reviews.llvm.org/D129735 fixes the issue that caused it to be disabled.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D145546
2023-03-08 23:03:35 -08:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck --check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck --check-prefixes=CHECK,RV64 %s
; Integers
define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
; RV32-LABEL: vector_deinterleave_v16i1_v32i1:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: .cfi_def_cfa_offset 32
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vfirst.m a0, v0
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: sb a0, 16(sp)
; RV32-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV32-NEXT: vmv.x.s a0, v0
; RV32-NEXT: slli a1, a0, 17
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 23(sp)
; RV32-NEXT: slli a1, a0, 19
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 22(sp)
; RV32-NEXT: slli a1, a0, 21
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 21(sp)
; RV32-NEXT: slli a1, a0, 23
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 20(sp)
; RV32-NEXT: slli a1, a0, 25
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 19(sp)
; RV32-NEXT: slli a1, a0, 27
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 18(sp)
; RV32-NEXT: slli a1, a0, 29
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 17(sp)
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v8, v0, 2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vfirst.m a1, v8
; RV32-NEXT: seqz a1, a1
; RV32-NEXT: sb a1, 24(sp)
; RV32-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: slli a2, a1, 17
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 31(sp)
; RV32-NEXT: slli a2, a1, 19
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 30(sp)
; RV32-NEXT: slli a2, a1, 21
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 29(sp)
; RV32-NEXT: slli a2, a1, 23
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 28(sp)
; RV32-NEXT: slli a2, a1, 25
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 27(sp)
; RV32-NEXT: slli a2, a1, 27
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 26(sp)
; RV32-NEXT: slli a2, a1, 29
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 25(sp)
; RV32-NEXT: slli a2, a0, 16
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 7(sp)
; RV32-NEXT: slli a2, a0, 18
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 6(sp)
; RV32-NEXT: slli a2, a0, 20
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 5(sp)
; RV32-NEXT: slli a2, a0, 22
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 4(sp)
; RV32-NEXT: slli a2, a0, 24
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 3(sp)
; RV32-NEXT: slli a2, a0, 26
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 2(sp)
; RV32-NEXT: slli a2, a0, 28
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: sb a2, 1(sp)
; RV32-NEXT: slli a0, a0, 30
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 0(sp)
; RV32-NEXT: slli a0, a1, 16
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 15(sp)
; RV32-NEXT: slli a0, a1, 18
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 14(sp)
; RV32-NEXT: slli a0, a1, 20
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 13(sp)
; RV32-NEXT: slli a0, a1, 22
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 12(sp)
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 11(sp)
; RV32-NEXT: slli a0, a1, 26
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 10(sp)
; RV32-NEXT: slli a0, a1, 28
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: sb a0, 9(sp)
; RV32-NEXT: slli a1, a1, 30
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: sb a1, 8(sp)
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: mv a0, sp
; RV32-NEXT: vle8.v v9, (a0)
; RV32-NEXT: vand.vi v8, v8, 1
; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: vand.vi v8, v9, 1
; RV32-NEXT: vmsne.vi v8, v8, 0
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
;
; RV64-LABEL: vector_deinterleave_v16i1_v32i1:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -32
; RV64-NEXT: .cfi_def_cfa_offset 32
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vfirst.m a0, v0
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: sb a0, 16(sp)
; RV64-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-NEXT: vmv.x.s a0, v0
; RV64-NEXT: slli a1, a0, 49
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 23(sp)
; RV64-NEXT: slli a1, a0, 51
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 22(sp)
; RV64-NEXT: slli a1, a0, 53
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 21(sp)
; RV64-NEXT: slli a1, a0, 55
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 20(sp)
; RV64-NEXT: slli a1, a0, 57
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 19(sp)
; RV64-NEXT: slli a1, a0, 59
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 18(sp)
; RV64-NEXT: slli a1, a0, 61
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 17(sp)
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v8, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vfirst.m a1, v8
; RV64-NEXT: seqz a1, a1
; RV64-NEXT: sb a1, 24(sp)
; RV64-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: slli a2, a1, 49
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 31(sp)
; RV64-NEXT: slli a2, a1, 51
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 30(sp)
; RV64-NEXT: slli a2, a1, 53
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 29(sp)
; RV64-NEXT: slli a2, a1, 55
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 28(sp)
; RV64-NEXT: slli a2, a1, 57
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 27(sp)
; RV64-NEXT: slli a2, a1, 59
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 26(sp)
; RV64-NEXT: slli a2, a1, 61
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 25(sp)
; RV64-NEXT: slli a2, a0, 48
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 7(sp)
; RV64-NEXT: slli a2, a0, 50
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 6(sp)
; RV64-NEXT: slli a2, a0, 52
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 5(sp)
; RV64-NEXT: slli a2, a0, 54
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 4(sp)
; RV64-NEXT: slli a2, a0, 56
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 3(sp)
; RV64-NEXT: slli a2, a0, 58
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 2(sp)
; RV64-NEXT: slli a2, a0, 60
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: sb a2, 1(sp)
; RV64-NEXT: slli a0, a0, 62
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 0(sp)
; RV64-NEXT: slli a0, a1, 48
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 15(sp)
; RV64-NEXT: slli a0, a1, 50
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 14(sp)
; RV64-NEXT: slli a0, a1, 52
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 13(sp)
; RV64-NEXT: slli a0, a1, 54
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 12(sp)
; RV64-NEXT: slli a0, a1, 56
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 11(sp)
; RV64-NEXT: slli a0, a1, 58
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 10(sp)
; RV64-NEXT: slli a0, a1, 60
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 9(sp)
; RV64-NEXT: slli a1, a1, 62
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: sb a1, 8(sp)
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: mv a0, sp
; RV64-NEXT: vle8.v v9, (a0)
; RV64-NEXT: vand.vi v8, v8, 1
; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: vand.vi v8, v9, 1
; RV64-NEXT: vmsne.vi v8, v8, 0
; RV64-NEXT: addi sp, sp, 32
; RV64-NEXT: ret
%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec)
ret {<16 x i1>, <16 x i1>} %retval
}
define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v11, v8, 8
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: vmv.v.v v9, v11
; CHECK-NEXT: ret
%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec)
ret {<16 x i8>, <16 x i8>} %retval
}
define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v11, v8, 16
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: vmv.v.v v9, v11
; CHECK-NEXT: ret
%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
ret {<8 x i16>, <8 x i16>} %retval
}
define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_vv8i32(<8 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave_v4i32_vv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wx v10, v8, a0
; CHECK-NEXT: vnsrl.wi v11, v8, 0
; CHECK-NEXT: vmv.v.v v8, v11
; CHECK-NEXT: vmv.v.v v9, v10
; CHECK-NEXT: ret
%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
ret {<4 x i32>, <4 x i32>} %retval
}
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: li a0, 2
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 0
; CHECK-NEXT: vrgather.vi v10, v12, 0, v0.t
; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vrgather.vi v9, v12, 1, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval
}
declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>)
declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>)
declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>)
; Floats
define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v8, 16
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec)
ret {<2 x half>, <2 x half>} %retval
}
define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v8, 16
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec)
ret {<4 x half>, <4 x half>} %retval
}
define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wx v9, v8, a0
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec)
ret {<2 x float>, <2 x float>} %retval
}
define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v11, v8, 16
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: vmv.v.v v9, v11
; CHECK-NEXT: ret
%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec)
ret {<8 x half>, <8 x half>} %retval
}
define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wx v10, v8, a0
; CHECK-NEXT: vnsrl.wi v11, v8, 0
; CHECK-NEXT: vmv.v.v v8, v11
; CHECK-NEXT: vmv.v.v v9, v10
; CHECK-NEXT: ret
%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
ret {<4 x float>, <4 x float>} %retval
}
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: li a0, 2
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 0
; CHECK-NEXT: vrgather.vi v10, v12, 0, v0.t
; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vrgather.vi v9, v12, 1, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval
}
declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)
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