86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
284 lines
7.7 KiB
LLVM
284 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,NOMISALIGN,RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,NOMISALIGN,RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,MISALIGN,MISALIGN-RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,MISALIGN,MISALIGN-RV64I %s
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; A collection of cases showing codegen for unaligned loads and stores
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define i8 @load_i8(ptr %p) {
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; ALL-LABEL: load_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: lb a0, 0(a0)
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; ALL-NEXT: ret
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%res = load i8, ptr %p, align 1
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ret i8 %res
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}
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define i16 @load_i16(ptr %p) {
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; NOMISALIGN-LABEL: load_i16:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: lb a1, 1(a0)
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; NOMISALIGN-NEXT: lbu a0, 0(a0)
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; NOMISALIGN-NEXT: slli a1, a1, 8
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; NOMISALIGN-NEXT: or a0, a1, a0
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: load_i16:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: lh a0, 0(a0)
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; MISALIGN-NEXT: ret
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%res = load i16, ptr %p, align 1
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ret i16 %res
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}
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define i24 @load_i24(ptr %p) {
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; NOMISALIGN-LABEL: load_i24:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: lbu a1, 1(a0)
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; NOMISALIGN-NEXT: lbu a2, 0(a0)
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; NOMISALIGN-NEXT: lb a0, 2(a0)
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; NOMISALIGN-NEXT: slli a1, a1, 8
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; NOMISALIGN-NEXT: or a1, a1, a2
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; NOMISALIGN-NEXT: slli a0, a0, 16
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; NOMISALIGN-NEXT: or a0, a1, a0
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: load_i24:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: lb a1, 2(a0)
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; MISALIGN-NEXT: lhu a0, 0(a0)
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; MISALIGN-NEXT: slli a1, a1, 16
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; MISALIGN-NEXT: or a0, a0, a1
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; MISALIGN-NEXT: ret
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%res = load i24, ptr %p, align 1
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ret i24 %res
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}
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define i32 @load_i32(ptr %p) {
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; RV32I-LABEL: load_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a2, 0(a0)
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; RV32I-NEXT: lbu a3, 2(a0)
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; RV32I-NEXT: lbu a0, 3(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: slli a3, a3, 16
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a2, 0(a0)
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; RV64I-NEXT: lbu a3, 2(a0)
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; RV64I-NEXT: lb a0, 3(a0)
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a3, a3, 16
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; RV64I-NEXT: slli a0, a0, 24
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; RV64I-NEXT: or a0, a0, a3
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; MISALIGN-LABEL: load_i32:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: lw a0, 0(a0)
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; MISALIGN-NEXT: ret
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%res = load i32, ptr %p, align 1
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ret i32 %res
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}
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define i64 @load_i64(ptr %p) {
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; RV32I-LABEL: load_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a2, 0(a0)
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; RV32I-NEXT: lbu a3, 2(a0)
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; RV32I-NEXT: lbu a4, 3(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: slli a3, a3, 16
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; RV32I-NEXT: slli a4, a4, 24
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; RV32I-NEXT: or a2, a4, a3
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; RV32I-NEXT: or a2, a2, a1
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; RV32I-NEXT: lbu a1, 5(a0)
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; RV32I-NEXT: lbu a3, 4(a0)
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; RV32I-NEXT: lbu a4, 6(a0)
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; RV32I-NEXT: lbu a0, 7(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: slli a4, a4, 16
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; RV32I-NEXT: slli a0, a0, 24
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; RV32I-NEXT: or a0, a0, a4
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; RV32I-NEXT: or a1, a0, a1
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a2, 0(a0)
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; RV64I-NEXT: lbu a3, 2(a0)
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; RV64I-NEXT: lbu a4, 3(a0)
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a3, a3, 16
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; RV64I-NEXT: slli a4, a4, 24
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; RV64I-NEXT: or a3, a4, a3
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; RV64I-NEXT: or a1, a3, a1
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; RV64I-NEXT: lbu a2, 5(a0)
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; RV64I-NEXT: lbu a3, 4(a0)
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; RV64I-NEXT: lbu a4, 6(a0)
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; RV64I-NEXT: lbu a0, 7(a0)
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; RV64I-NEXT: slli a2, a2, 8
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; RV64I-NEXT: or a2, a2, a3
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; RV64I-NEXT: slli a4, a4, 16
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; RV64I-NEXT: slli a0, a0, 24
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; RV64I-NEXT: or a0, a0, a4
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; MISALIGN-RV32I-LABEL: load_i64:
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; MISALIGN-RV32I: # %bb.0:
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; MISALIGN-RV32I-NEXT: lw a2, 0(a0)
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; MISALIGN-RV32I-NEXT: lw a1, 4(a0)
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; MISALIGN-RV32I-NEXT: mv a0, a2
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; MISALIGN-RV32I-NEXT: ret
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;
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; MISALIGN-RV64I-LABEL: load_i64:
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; MISALIGN-RV64I: # %bb.0:
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; MISALIGN-RV64I-NEXT: ld a0, 0(a0)
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; MISALIGN-RV64I-NEXT: ret
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%res = load i64, ptr %p, align 1
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ret i64 %res
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}
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define void @store_i8(ptr %p, i8 %v) {
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; ALL-LABEL: store_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: sb a1, 0(a0)
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; ALL-NEXT: ret
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store i8 %v, ptr %p, align 1
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ret void
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}
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define void @store_i16(ptr %p, i16 %v) {
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; NOMISALIGN-LABEL: store_i16:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: sb a1, 0(a0)
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; NOMISALIGN-NEXT: srli a1, a1, 8
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; NOMISALIGN-NEXT: sb a1, 1(a0)
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: store_i16:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: sh a1, 0(a0)
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; MISALIGN-NEXT: ret
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store i16 %v, ptr %p, align 1
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ret void
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}
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define void @store_i24(ptr %p, i24 %v) {
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; NOMISALIGN-LABEL: store_i24:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: sb a1, 0(a0)
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; NOMISALIGN-NEXT: srli a2, a1, 8
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; NOMISALIGN-NEXT: sb a2, 1(a0)
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; NOMISALIGN-NEXT: srli a1, a1, 16
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; NOMISALIGN-NEXT: sb a1, 2(a0)
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: store_i24:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: sh a1, 0(a0)
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; MISALIGN-NEXT: srli a1, a1, 16
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; MISALIGN-NEXT: sb a1, 2(a0)
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; MISALIGN-NEXT: ret
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store i24 %v, ptr %p, align 1
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ret void
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}
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define void @store_i32(ptr %p, i32 %v) {
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; NOMISALIGN-LABEL: store_i32:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: sb a1, 0(a0)
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; NOMISALIGN-NEXT: srli a2, a1, 24
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; NOMISALIGN-NEXT: sb a2, 3(a0)
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; NOMISALIGN-NEXT: srli a2, a1, 16
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; NOMISALIGN-NEXT: sb a2, 2(a0)
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; NOMISALIGN-NEXT: srli a1, a1, 8
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; NOMISALIGN-NEXT: sb a1, 1(a0)
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: store_i32:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: sw a1, 0(a0)
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; MISALIGN-NEXT: ret
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store i32 %v, ptr %p, align 1
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ret void
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}
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define void @store_i64(ptr %p, i64 %v) {
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; RV32I-LABEL: store_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sb a2, 4(a0)
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: srli a3, a2, 24
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; RV32I-NEXT: sb a3, 7(a0)
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; RV32I-NEXT: srli a3, a2, 16
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; RV32I-NEXT: sb a3, 6(a0)
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; RV32I-NEXT: srli a2, a2, 8
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; RV32I-NEXT: sb a2, 5(a0)
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; RV32I-NEXT: srli a2, a1, 24
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; RV32I-NEXT: sb a2, 3(a0)
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; RV32I-NEXT: srli a2, a1, 16
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; RV32I-NEXT: sb a2, 2(a0)
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; RV32I-NEXT: srli a1, a1, 8
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; RV32I-NEXT: sb a1, 1(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: store_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sb a1, 0(a0)
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; RV64I-NEXT: srli a2, a1, 56
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; RV64I-NEXT: sb a2, 7(a0)
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; RV64I-NEXT: srli a2, a1, 48
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; RV64I-NEXT: sb a2, 6(a0)
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; RV64I-NEXT: srli a2, a1, 40
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; RV64I-NEXT: sb a2, 5(a0)
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; RV64I-NEXT: srli a2, a1, 32
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; RV64I-NEXT: sb a2, 4(a0)
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; RV64I-NEXT: srli a2, a1, 24
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; RV64I-NEXT: sb a2, 3(a0)
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; RV64I-NEXT: srli a2, a1, 16
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; RV64I-NEXT: sb a2, 2(a0)
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; RV64I-NEXT: srli a1, a1, 8
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; RV64I-NEXT: sb a1, 1(a0)
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; RV64I-NEXT: ret
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;
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; MISALIGN-RV32I-LABEL: store_i64:
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; MISALIGN-RV32I: # %bb.0:
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; MISALIGN-RV32I-NEXT: sw a2, 4(a0)
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; MISALIGN-RV32I-NEXT: sw a1, 0(a0)
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; MISALIGN-RV32I-NEXT: ret
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;
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; MISALIGN-RV64I-LABEL: store_i64:
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; MISALIGN-RV64I: # %bb.0:
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; MISALIGN-RV64I-NEXT: sd a1, 0(a0)
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; MISALIGN-RV64I-NEXT: ret
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store i64 %v, ptr %p, align 1
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ret void
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}
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