dfa54298ff
The InitUndef pass works around a register allocation issue, where undef operands can be allocated to the same register as early-clobber result operands. This may lead to ISA constraint violations, where certain input and output registers are not allowed to overlap. Originally this pass was implemented for RISCV, and then extended to ARM in #77770. I've since removed the target-specific parts of the pass in #106744 and #107885. This PR reduces the pass to use a single requiresDisjointEarlyClobberAndUndef() target hook and enables it by default. The hook is disabled for AMDGPU, because overlapping early-clobber and undef operands are known to be safe for that target, and we get significant codegen diffs otherwise. The motivating case is the one in arm64-ldxr-stxr.ll, where we were previously incorrectly allocating a stxp input and output to the same register.
313 lines
11 KiB
C++
313 lines
11 KiB
C++
//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
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#include "GISel/RISCVRegisterBankInfo.h"
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCVFrameLowering.h"
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#include "RISCVISelLowering.h"
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#include "RISCVInstrInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#include <bitset>
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#define GET_RISCV_MACRO_FUSION_PRED_DECL
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#include "RISCVGenMacroFusion.inc"
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#define GET_SUBTARGETINFO_HEADER
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#include "RISCVGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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namespace RISCVTuneInfoTable {
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struct RISCVTuneInfo {
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const char *Name;
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uint8_t PrefFunctionAlignment;
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uint8_t PrefLoopAlignment;
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// Information needed by LoopDataPrefetch.
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uint16_t CacheLineSize;
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uint16_t PrefetchDistance;
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uint16_t MinPrefetchStride;
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unsigned MaxPrefetchIterationsAhead;
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unsigned MinimumJumpTableEntries;
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// Tail duplication threshold at -O3.
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unsigned TailDupAggressiveThreshold;
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};
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#define GET_RISCVTuneInfoTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // namespace RISCVTuneInfoTable
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class RISCVSubtarget : public RISCVGenSubtargetInfo {
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public:
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// clang-format off
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enum RISCVProcFamilyEnum : uint8_t {
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Others,
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SiFive7,
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VentanaVeyron,
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};
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// clang-format on
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private:
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virtual void anchor();
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RISCVProcFamilyEnum RISCVProcFamily = Others;
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "RISCVGenSubtargetInfo.inc"
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unsigned ZvlLen = 0;
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unsigned RVVVectorBitsMin;
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unsigned RVVVectorBitsMax;
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uint8_t MaxInterleaveFactor = 2;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
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const RISCVTuneInfoTable::RISCVTuneInfo *TuneInfo;
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RISCVFrameLowering FrameLowering;
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RISCVInstrInfo InstrInfo;
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RISCVRegisterInfo RegInfo;
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RISCVTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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/// Initializes using the passed in CPU and feature strings so that we can
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/// use initializer lists for subtarget initialization.
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RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef CPU,
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StringRef TuneCPU,
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StringRef FS,
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StringRef ABIName);
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public:
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// Initializes the data members to match that of the specified triple.
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RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
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StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
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unsigned RVVVectorLMULMax, const TargetMachine &TM);
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// Parses features string setting specified subtarget options. The
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// definition of this function is auto-generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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const RISCVFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const RISCVRegisterInfo *getRegisterInfo() const override {
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return &RegInfo;
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}
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const RISCVTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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bool enableMachineScheduler() const override { return true; }
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bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
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Align getPrefFunctionAlignment() const {
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return Align(TuneInfo->PrefFunctionAlignment);
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}
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Align getPrefLoopAlignment() const {
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return Align(TuneInfo->PrefLoopAlignment);
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}
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/// Returns RISC-V processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool GETTER() const { return ATTRIBUTE; }
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#include "RISCVGenSubtargetInfo.inc"
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bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
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bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
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bool hasStdExtCOrZcfOrZce() const {
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return HasStdExtC || HasStdExtZcf || HasStdExtZce;
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}
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bool hasStdExtZvl() const { return ZvlLen != 0; }
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bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
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bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
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bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
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bool hasStdExtZfhminOrZhinxmin() const {
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return HasStdExtZfhmin || HasStdExtZhinxmin;
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}
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bool hasHalfFPLoadStoreMove() const {
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return HasStdExtZfhmin || HasStdExtZfbfmin;
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}
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bool hasConditionalMoveFusion() const {
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// Do we support fusing a branch+mv or branch+c.mv as a conditional move.
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return (hasConditionalCompressedMoveFusion() && hasStdExtCOrZca()) ||
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hasShortForwardBranchOpt();
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}
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bool is64Bit() const { return IsRV64; }
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MVT getXLenVT() const {
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return is64Bit() ? MVT::i64 : MVT::i32;
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}
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unsigned getXLen() const {
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return is64Bit() ? 64 : 32;
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}
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unsigned getFLen() const {
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if (HasStdExtD)
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return 64;
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if (HasStdExtF)
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return 32;
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return 0;
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}
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unsigned getELen() const {
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assert(hasVInstructions() && "Expected V extension");
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return hasVInstructionsI64() ? 64 : 32;
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}
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unsigned getRealMinVLen() const {
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unsigned VLen = getMinRVVVectorSizeInBits();
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return VLen == 0 ? ZvlLen : VLen;
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}
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unsigned getRealMaxVLen() const {
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unsigned VLen = getMaxRVVVectorSizeInBits();
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return VLen == 0 ? 65536 : VLen;
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}
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// If we know the exact VLEN, return it. Otherwise, return std::nullopt.
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std::optional<unsigned> getRealVLen() const {
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unsigned Min = getRealMinVLen();
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if (Min != getRealMaxVLen())
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return std::nullopt;
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return Min;
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}
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/// If the ElementCount or TypeSize \p X is scalable and VScale (VLEN) is
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/// exactly known, returns \p X converted to a fixed quantity. Otherwise
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/// returns \p X unmodified.
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template <typename Quantity> Quantity expandVScale(Quantity X) const {
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if (auto VLen = getRealVLen(); VLen && X.isScalable()) {
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const unsigned VScale = *VLen / RISCV::RVVBitsPerBlock;
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X = Quantity::getFixed(X.getKnownMinValue() * VScale);
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}
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return X;
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}
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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bool isSoftFPABI() const {
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return TargetABI == RISCVABI::ABI_LP64 ||
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TargetABI == RISCVABI::ABI_ILP32 ||
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TargetABI == RISCVABI::ABI_ILP32E;
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}
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bool isRegisterReservedByUser(Register i) const {
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assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
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return UserReservedRegister[i];
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}
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// Vector codegen related methods.
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bool hasVInstructions() const { return HasStdExtZve32x; }
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bool hasVInstructionsI64() const { return HasStdExtZve64x; }
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bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
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bool hasVInstructionsF16() const { return HasStdExtZvfh; }
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bool hasVInstructionsBF16Minimal() const { return HasStdExtZvfbfmin; }
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bool hasVInstructionsF32() const { return HasStdExtZve32f; }
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bool hasVInstructionsF64() const { return HasStdExtZve64d; }
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// F16 and F64 both require F32.
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bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
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bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
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unsigned getMaxInterleaveFactor() const {
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return hasVInstructions() ? MaxInterleaveFactor : 1;
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}
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// Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
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// vector hardware implementation which may be less than VLEN.
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unsigned getDLenFactor() const {
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if (DLenFactor2)
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return 2;
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return 1;
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}
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protected:
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// GlobalISel related APIs.
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mutable std::unique_ptr<CallLowering> CallLoweringInfo;
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mutable std::unique_ptr<InstructionSelector> InstSelector;
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mutable std::unique_ptr<LegalizerInfo> Legalizer;
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mutable std::unique_ptr<RISCVRegisterBankInfo> RegBankInfo;
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// Return the known range for the bit length of RVV data registers as set
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// at the command line. A value of 0 means nothing is known about that particular
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// limit beyond what's implied by the architecture.
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// NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
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unsigned getMaxRVVVectorSizeInBits() const;
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unsigned getMinRVVVectorSizeInBits() const;
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public:
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const CallLowering *getCallLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RISCVRegisterBankInfo *getRegBankInfo() const override;
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bool isTargetAndroid() const { return getTargetTriple().isAndroid(); }
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bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
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bool useConstantPoolForLargeInts() const;
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// Maximum cost used for building integers, integers will be put into constant
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// pool if exceeded.
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unsigned getMaxBuildIntsCost() const;
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unsigned getMaxLMULForFixedLengthVectors() const;
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bool useRVVForFixedLengthVectors() const;
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bool enableSubRegLiveness() const override;
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void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
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&Mutations) const override;
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bool useAA() const override;
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unsigned getCacheLineSize() const override {
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return TuneInfo->CacheLineSize;
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};
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unsigned getPrefetchDistance() const override {
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return TuneInfo->PrefetchDistance;
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};
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unsigned getMinPrefetchStride(unsigned NumMemAccesses,
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unsigned NumStridedMemAccesses,
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unsigned NumPrefetches,
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bool HasCall) const override {
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return TuneInfo->MinPrefetchStride;
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};
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unsigned getMaxPrefetchIterationsAhead() const override {
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return TuneInfo->MaxPrefetchIterationsAhead;
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};
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unsigned getMinimumJumpTableEntries() const;
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unsigned getTailDupAggressiveThreshold() const {
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return TuneInfo->TailDupAggressiveThreshold;
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}
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};
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} // End llvm namespace
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#endif
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