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llvm-project/llvm/lib/Target/RISCV
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Luke Lau 5eb7191421 [RISCV] Add VP patterns for vandn.[vv,vx] 
This builds upon D155433

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155434
2023-07-18 13:53:17 +01:00
..
AsmParser
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
Disassembler
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
GISel
[RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
2023-07-14 18:22:53 -07:00
MCA
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
MCTargetDesc
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.h
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add new lga pseudoinstruction
2023-05-31 18:48:21 +01:00
RISCVFeatures.td
[RISCV] Remove 'not FeatureStdExtC' from Zcmp predicate.
2023-07-17 09:12:54 -07:00
RISCVFrameLowering.cpp
[RISCV] Readjusting the framestack for Zcmp
2023-07-07 11:24:21 +08:00
RISCVFrameLowering.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
RISCVInstrFormats.td
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
RISCVInstrFormatsC.td
Recommit "[RISCV] Add .insn support for compressed formats."
2023-03-27 12:30:37 -07:00
RISCVInstrFormatsV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrInfo.cpp
[RISCV] Adjust the Zfhmin handling in RISCVInstrInfo::copyPhysReg.
2023-07-16 20:20:59 -07:00
RISCVInstrInfo.h
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVInstrInfo.td
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
RISCVInstrInfoA.td
[RISCV][MC] MC layer support for the experimental zacas extension
2023-07-10 08:26:31 +01:00
RISCVInstrInfoC.td
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
RISCVInstrInfoD.td
[RISCV] Add bf16 as a valid type for the FPR16 register class.
2023-07-17 08:30:40 -07:00
RISCVInstrInfoF.td
[RISCV] Add bf16 as a valid type for the FPR16 register class.
2023-07-17 08:30:40 -07:00
RISCVInstrInfoM.td
[RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
2022-12-14 10:38:48 -08:00
RISCVInstrInfoV.td
[RISCV] Add initial SDNode patterns for unary zvbb instructions
2023-07-13 19:39:04 +01:00
RISCVInstrInfoVPseudos.td
[RISCV] Add SEW to RISCVInversePseudoTable
2023-07-14 12:12:03 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add bf16 as a valid type for the FPR16 register class.
2023-07-17 08:30:40 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add VL nodes and VP patterns for unary zvbb instructions
2023-07-17 09:17:58 +01:00
RISCVInstrInfoXCV.td
[RISCV] Fix 80 column violations in RISCVInstrInfoXCV.td. NFC
2023-07-04 18:58:32 -07:00
RISCVInstrInfoXSf.td
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Use GPR register class for RV64 ZDInx. Remove GPRF64 register class.
2023-06-22 09:38:46 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Use GPR register class for RV64 ZDInx. Remove GPRF64 register class.
2023-06-22 09:38:46 -07:00
RISCVInstrInfoZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVInstrInfoZc.td
[RISCV] Fix encoding for Zcb instruction c.sh.
2023-06-27 09:44:50 -07:00
RISCVInstrInfoZfa.td
[RISCV] Add bf16 as a valid type for the FPR16 register class.
2023-07-17 08:30:40 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV][MC] Add support for experimental Zfbfmin extension
2023-05-19 15:17:56 +01:00
RISCVInstrInfoZfh.td
[RISCV] Add bf16 as a valid type for the FPR16 register class.
2023-07-17 08:30:40 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Add support for llvm.prefetch to use Zicbop instructions.
2023-06-13 09:51:30 -07:00
RISCVInstrInfoZicond.td
[RISCV] Introduce RISCVISD::CZERO_{EQZ,NEZ} nodes produce them when zicond is present in lowerSELECT
2023-07-14 11:31:27 +01:00
RISCVInstrInfoZk.td
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
RISCVInstrInfoZvfbf.td
[RISCV][MC] Fix encoding for vfwmaccbf16
2023-06-23 14:01:52 +01:00
RISCVInstrInfoZvk.td
[RISCV] Add VP patterns for vandn.[vv,vx]
2023-07-18 13:53:17 +01:00
RISCVISelDAGToDAG.cpp
[RISCV] Implement prefetch locality by NTLH
2023-07-16 20:32:46 -07:00
RISCVISelDAGToDAG.h
[RISCV] Remove legacy TA/TU pseudo distinction of vmerge and carry-in arithmetic operations [NFC[
2023-07-12 15:31:02 -07:00
RISCVISelLowering.cpp
[RISCV] Lower VP_CTLZ_ZERO_UNDEF/VP_CTTZ_ZERO_UNDEF/VP_CTLZ by converting to FP and extracting the exponent.
2023-07-18 15:25:59 +08:00
RISCVISelLowering.h
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Remove unused private field 'RVPushable' in RISCVMachineFunctionInfo.h
2023-07-07 11:35:48 +08:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMergeBaseOffset.cpp
[RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.
2023-07-11 09:53:56 -07:00
RISCVMoveMerger.cpp
[RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style
2023-06-27 13:35:41 +01:00
RISCVOptWInstrs.cpp
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVProcessors.td
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
RISCVPushPopOptimizer.cpp
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[RISCV] Readjusting the framestack for Zcmp
2023-07-07 11:24:21 +08:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV] Add bf16 as a valid type for the FPR16 register class.
2023-07-17 08:30:40 -07:00
RISCVRVVInitUndef.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVSchedRocket.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVSchedSiFive7.td
[RISCV] Correct resource cycles for vzext/vsext in SiFive7 scheduler.
2023-07-13 11:37:21 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVSchedule.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVScheduleV.td
[RISCV] Split scheduler class for integer min/max reduction from other integer reductions. NFC
2023-07-12 12:58:01 -07:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2023-06-02 23:14:17 -07:00
RISCVSubtarget.h
[RISCV] Introduce the concept of DLEN(data path width) into getLMULCost.
2023-06-13 16:09:25 -07:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCVTargetMachine.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores
2023-07-07 15:34:24 +01:00
RISCVTargetTransformInfo.h
[CostModel] Use min/max intrinsics for vecreduce.min/max costs
2023-07-04 15:02:30 +01:00