689db42c9c
1. Move all pattern fragments for SIMD instructions to X86InstrFragmentsSIMD.td 2. Create X86InstrFragments.td and move non-SIMD pattern fragments into it 3. Create X86InstrOperands.td and move operand definitions into it 4. Create X86InstrPredicates.td and move predicate definitions into it 5. Create X86InstrUtils.td and move utilities for simplifying the instruction definitions into it
103 lines
5.0 KiB
TableGen
103 lines
5.0 KiB
TableGen
//===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the 3DNow! instruction set, which extends MMX to support
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// floating point and also adds a few more random instructions for good measure.
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//
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//===----------------------------------------------------------------------===//
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class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat>
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: I<o, F, outs, ins, asm, pat>, Requires<[Has3DNow]> {
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}
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class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
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: I3DNow<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>, ThreeDNow {
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let Constraints = "$src1 = $dst";
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}
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class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
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: I3DNow<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, ThreeDNow;
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multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn,
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X86FoldableSchedWrite sched, bit Commutable = 0,
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string Ver = ""> {
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let isCommutable = Commutable in
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def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>,
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Sched<[sched]>;
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def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn,
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X86FoldableSchedWrite sched, string Ver = ""> {
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def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>,
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Sched<[sched]>;
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def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn))
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(bitconvert (load_mmx addr:$src))))]>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>;
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defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtPS2I>;
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defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>;
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defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>;
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defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>;
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defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>;
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defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>;
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defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>;
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defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>;
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defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>;
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defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>;
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defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>;
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defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>;
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defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>;
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defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>;
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defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>;
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defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>;
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defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>;
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defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>;
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let SchedRW = [WriteEMMS],
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Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
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def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
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[(int_x86_mmx_femms)]>, TB;
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let SchedRW = [WriteLoad] in {
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let Predicates = [Has3DNow, NoSSEPrefetch] in
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def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
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"prefetch\t$addr",
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[(prefetch addr:$addr, timm, timm, (i32 1))]>, TB;
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def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
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[(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>,
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TB, Requires<[HasPrefetchW]>;
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def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr",
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[(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))]>,
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TB, Requires<[HasPREFETCHWT1]>;
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}
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// "3DNowA" instructions
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defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtPS2I, "a">;
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defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2PS, "a">;
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defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">;
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defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">;
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defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">;
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