697beb3f17
Add LLVM Context to getOptimalMemOpType and findOptimalMemOpLowering. So that we can use EVT::getVectorVT to generate EVT type in getOptimalMemOpType. Related to [#146673](https://github.com/llvm/llvm-project/pull/146673).
662 lines
31 KiB
C++
662 lines
31 KiB
C++
//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that RISC-V uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#include "RISCV.h"
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#include "RISCVCallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include <optional>
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namespace llvm {
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class InstructionCost;
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class RISCVSubtarget;
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struct RISCVRegisterInfo;
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class RISCVTargetLowering : public TargetLowering {
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const RISCVSubtarget &Subtarget;
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public:
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explicit RISCVTargetLowering(const TargetMachine &TM,
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const RISCVSubtarget &STI);
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const RISCVSubtarget &getSubtarget() const { return Subtarget; }
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool isLegalICmpImmediate(int64_t Imm) const override;
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bool isLegalAddImmediate(int64_t Imm) const override;
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bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
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bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
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bool isTruncateFree(SDValue Val, EVT VT2) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
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bool signExtendConstant(const ConstantInt *CI) const override;
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bool isCheapToSpeculateCttz(Type *Ty) const override;
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bool isCheapToSpeculateCtlz(Type *Ty) const override;
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bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
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bool hasAndNotCompare(SDValue Y) const override;
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bool hasAndNot(SDValue Y) const override;
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bool hasBitTest(SDValue X, SDValue Y) const override;
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bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
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SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
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unsigned OldShiftOpcode, unsigned NewShiftOpcode,
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SelectionDAG &DAG) const override;
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bool shouldScalarizeBinop(SDValue VecOp) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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unsigned Index) const override;
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bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
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bool preferScalarizeSplat(SDNode *N) const override;
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bool softPromoteHalfType() const override { return true; }
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/// Return the register type for a given MVT, ensuring vectors are treated
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/// as a series of gpr sized integers.
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MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
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EVT VT) const override;
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/// Return the number of registers for a given MVT, for inline assembly
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unsigned
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getNumRegisters(LLVMContext &Context, EVT VT,
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std::optional<MVT> RegisterVT = std::nullopt) const override;
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/// Return the number of registers for a given MVT, ensuring vectors are
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/// treated as a series of gpr sized integers.
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
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CallingConv::ID CC, EVT VT,
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EVT &IntermediateVT,
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unsigned &NumIntermediates,
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MVT &RegisterVT) const override;
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bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
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unsigned SelectOpcode, SDValue X,
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SDValue Y) const override;
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/// Return true if the given shuffle mask can be codegen'd directly, or if it
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/// should be stack expanded.
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bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
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bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
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// If the pair to store is a mixture of float and int values, we will
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// save two bitwise instructions and one float-to-int instruction and
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// increase one store instruction. There is potentially a more
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// significant benefit because it avoids the float->int domain switch
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// for input value. So It is more likely a win.
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if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
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(LTy.isInteger() && HTy.isFloatingPoint()))
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return true;
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// If the pair only contains int values, we will save two bitwise
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// instructions and increase one store instruction (costing one more
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// store buffer). Since the benefit is more blurred we leave such a pair
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// out until we get testcase to prove it is a win.
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return false;
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}
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bool
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shouldExpandBuildVectorWithShuffles(EVT VT,
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unsigned DefinedValues) const override;
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bool shouldExpandCttzElements(EVT VT) const override;
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/// Return the cost of LMUL for linear operations.
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InstructionCost getLMULCost(MVT VT) const;
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InstructionCost getVRGatherVVCost(MVT VT) const;
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InstructionCost getVRGatherVICost(MVT VT) const;
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InstructionCost getVSlideVXCost(MVT VT) const;
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InstructionCost getVSlideVICost(MVT VT) const;
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
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const APInt &DemandedElts,
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TargetLoweringOpt &TLO) const override;
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void computeKnownBitsForTargetNode(const SDValue Op,
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KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits,
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const APInt &DemandedElts,
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KnownBits &Known,
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TargetLoweringOpt &TLO,
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unsigned Depth) const override;
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bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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bool PoisonOnly, bool ConsiderFlags,
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unsigned Depth) const override;
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const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
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MachineMemOperand::Flags
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getTargetMMOFlags(const Instruction &I) const override;
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MachineMemOperand::Flags
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getTargetMMOFlags(const MemSDNode &Node) const override;
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bool
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areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX,
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const MemSDNode &NodeY) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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InlineAsm::ConstraintCode
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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void AdjustInstrPostInstrSelection(MachineInstr &MI,
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SDNode *Node) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
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bool MathUsed) const override {
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if (VT == MVT::i8 || VT == MVT::i16)
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return false;
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return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
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}
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bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
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unsigned AddrSpace) const override {
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// If we can replace 4 or more scalar stores, there will be a reduction
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// in instructions even after we add a vector constant load.
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return NumElem >= 4;
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}
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bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
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return VT.isScalarInteger();
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}
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bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
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bool isCtpopFast(EVT VT) const override;
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unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
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bool preferZeroCompareBranch() const override { return true; }
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// Note that one specific case requires fence insertion for an
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// AtomicCmpXchgInst but is handled via the RISCVZacasABIFix pass rather
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// than this hook due to limitations in the interface here.
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bool shouldInsertFencesForAtomic(const Instruction *I) const override;
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Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT VT) const override;
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ISD::NodeType getExtendForAtomicOps() const override {
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return ISD::SIGN_EXTEND;
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}
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ISD::NodeType getExtendForAtomicCmpSwapArg() const override;
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bool shouldTransformSignedTruncationCheck(EVT XVT,
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unsigned KeptBits) const override;
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TargetLowering::ShiftLegalizationStrategy
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preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
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unsigned ExpansionFactor) const override {
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return ShiftLegalizationStrategy::LowerToLibcall;
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return TargetLowering::preferredShiftLegalizationStrategy(DAG, N,
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ExpansionFactor);
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}
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bool isDesirableToCommuteWithShift(const SDNode *N,
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CombineLevel Level) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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Register
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getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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Register
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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bool shouldExtendTypeInLibCall(EVT Type) const override;
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bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const override;
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/// Returns the register with the specified architectural or ABI name. This
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/// method is necessary to lower the llvm.read_register.* and
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/// llvm.write_register.* intrinsics. Allocatable registers must be reserved
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/// with the clang -ffixed-xX flag for access to be allowed.
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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// Lower incoming arguments, copy physregs into vregs
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context, const Type *RetTy) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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bool shouldConsiderGEPOffsetSplit() const override { return true; }
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bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
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SDValue C) const override;
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bool isMulAddWithConstProfitable(SDValue AddNode,
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SDValue ConstNode) const override;
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI,
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Value *AlignedAddr, Value *Incr,
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Value *Mask, Value *ShiftAmt,
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AtomicOrdering Ord) const override;
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
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Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder,
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AtomicCmpXchgInst *CI,
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Value *AlignedAddr, Value *CmpVal,
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Value *NewVal, Value *Mask,
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AtomicOrdering Ord) const override;
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/// Returns true if the target allows unaligned memory accesses of the
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/// specified type.
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bool allowsMisalignedMemoryAccesses(
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EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
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MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
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unsigned *Fast = nullptr) const override;
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EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
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const AttributeList &FuncAttributes) const override;
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bool splitValueIntoRegisterParts(
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SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
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unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
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const override;
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SDValue joinRegisterPartsIntoValue(
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SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
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unsigned NumParts, MVT PartVT, EVT ValueVT,
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std::optional<CallingConv::ID> CC) const override;
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// Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
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SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
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static RISCVVType::VLMUL getLMUL(MVT VT);
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inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
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unsigned MinSize) {
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// Original equation:
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// VLMAX = (VectorBits / EltSize) * LMUL
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// where LMUL = MinSize / RISCV::RVVBitsPerBlock
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// The following equations have been reordered to prevent loss of precision
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// when calculating fractional LMUL.
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return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
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}
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// Return inclusive (low, high) bounds on the value of VLMAX for the
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// given scalable container type given known bounds on VLEN.
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static std::pair<unsigned, unsigned>
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computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget);
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/// Given a vector (either fixed or scalable), return the scalable vector
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/// corresponding to a vector register (i.e. an m1 register group).
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static MVT getM1VT(MVT VT) {
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unsigned EltSizeInBits = VT.getVectorElementType().getSizeInBits();
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assert(EltSizeInBits <= RISCV::RVVBitsPerBlock && "Unexpected vector MVT");
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return MVT::getScalableVectorVT(VT.getVectorElementType(),
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RISCV::RVVBitsPerBlock / EltSizeInBits);
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}
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static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul);
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static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
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static unsigned getRegClassIDForVecVT(MVT VT);
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static std::pair<unsigned, unsigned>
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decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
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unsigned InsertExtractIdx,
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const RISCVRegisterInfo *TRI);
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MVT getContainerForFixedLengthVector(MVT VT) const;
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bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
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bool isLegalElementTypeForRVV(EVT ScalarTy) const;
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bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
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unsigned getJumpTableEncoding() const override;
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const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
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const MachineBasicBlock *MBB,
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unsigned uid,
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MCContext &Ctx) const override;
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bool isVScaleKnownToBeAPowerOfTwo() const override;
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bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
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bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
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SDValue &Offset, ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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bool isLegalScaleForGatherScatter(uint64_t Scale,
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uint64_t ElemSize) const override {
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// Scaled addressing not supported on indexed load/stores
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return Scale == 1;
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}
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/// If the target has a standard location for the stack protector cookie,
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/// returns the address of that location. Otherwise, returns nullptr.
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Value *getIRStackGuard(IRBuilderBase &IRB) const override;
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/// Returns whether or not generating a interleaved load/store intrinsic for
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/// this type will be legal.
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bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
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Align Alignment, unsigned AddrSpace,
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const DataLayout &) const;
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/// Return true if a stride load store of the given result type and
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/// alignment is legal.
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bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
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unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
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bool fallBackToDAGISel(const Instruction &Inst) const override;
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bool lowerInterleavedLoad(LoadInst *LI,
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ArrayRef<ShuffleVectorInst *> Shuffles,
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ArrayRef<unsigned> Indices,
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unsigned Factor) const override;
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bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
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unsigned Factor) const override;
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bool lowerDeinterleaveIntrinsicToLoad(
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LoadInst *LI, ArrayRef<Value *> DeinterleaveValues) const override;
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bool lowerInterleaveIntrinsicToStore(
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StoreInst *SI, ArrayRef<Value *> InterleaveValues) const override;
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bool lowerInterleavedVPLoad(VPIntrinsic *Load, Value *Mask,
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ArrayRef<Value *> DeinterleaveRes) const override;
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bool lowerInterleavedVPStore(VPIntrinsic *Store, Value *Mask,
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ArrayRef<Value *> InterleaveOps) const override;
|
|
|
|
bool supportKCFIBundles() const override { return true; }
|
|
|
|
SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr,
|
|
int JTI, SelectionDAG &DAG) const override;
|
|
|
|
MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::instr_iterator &MBBI,
|
|
const TargetInstrInfo *TII) const override;
|
|
|
|
/// True if stack clash protection is enabled for this functions.
|
|
bool hasInlineStackProbe(const MachineFunction &MF) const override;
|
|
|
|
unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const;
|
|
|
|
MachineBasicBlock *emitDynamicProbedAlloc(MachineInstr &MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
|
|
|
|
private:
|
|
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
|
|
RISCVCCAssignFn Fn) const;
|
|
void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
bool IsRet, CallLoweringInfo *CLI,
|
|
RISCVCCAssignFn Fn) const;
|
|
|
|
template <class NodeTy>
|
|
SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
|
|
bool IsExternWeak = false) const;
|
|
SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
|
|
bool UseGOT) const;
|
|
SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
|
|
SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerConstantFP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
|
|
SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
|
|
int64_t ExtTrueVal) const;
|
|
SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
|
|
bool IsVP) const;
|
|
SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVectorCompress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
|
|
SelectionDAG &DAG) const;
|
|
SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
|
|
SelectionDAG &DAG) const;
|
|
SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPMergeMask(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPSplatExperimental(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVPCttzElements(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
|
|
unsigned ExtendOpc) const;
|
|
SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerRESET_FPENV(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerPARTIAL_REDUCE_MLA(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
bool isEligibleForTailCallOptimization(
|
|
CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
|
|
const SmallVector<CCValAssign, 16> &ArgLocs) const;
|
|
|
|
/// Generate error diagnostics if any register used by CC has been marked
|
|
/// reserved.
|
|
void validateCCReservedRegs(
|
|
const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
|
|
MachineFunction &MF) const;
|
|
|
|
bool useRVVForFixedLengthVectorVT(MVT VT) const;
|
|
|
|
MVT getVPExplicitVectorLengthTy() const override;
|
|
|
|
bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
|
|
bool IsScalable) const override;
|
|
|
|
/// RVV code generation for fixed length vectors does not lower all
|
|
/// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
|
|
/// merge. However, merging them creates a BUILD_VECTOR that is just as
|
|
/// illegal as the original, thus leading to an infinite legalisation loop.
|
|
/// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
|
|
/// this override can be removed.
|
|
bool mergeStoresAfterLegalization(EVT VT) const override;
|
|
|
|
/// Disable normalizing
|
|
/// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
|
|
/// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
|
|
/// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
|
|
bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
|
|
return false;
|
|
}
|
|
|
|
/// Disables storing and loading vectors by default when there are function
|
|
/// calls between the load and store, since these are more expensive than just
|
|
/// using scalars
|
|
bool shouldMergeStoreOfLoadsOverCall(EVT SrcVT, EVT MergedVT) const override {
|
|
return !MergedVT.isVector() || SrcVT.isVector();
|
|
}
|
|
|
|
/// For available scheduling models FDIV + two independent FMULs are much
|
|
/// faster than two FDIVs.
|
|
unsigned combineRepeatedFPDivisors() const override;
|
|
|
|
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDNode *> &Created) const override;
|
|
|
|
bool shouldFoldSelectWithSingleBitTest(EVT VT,
|
|
const APInt &AndMask) const override;
|
|
|
|
unsigned getMinimumJumpTableEntries() const override;
|
|
|
|
SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
|
|
SDValue End, SDValue Flags, SDLoc DL) const;
|
|
|
|
std::pair<const TargetRegisterClass *, uint8_t>
|
|
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override;
|
|
};
|
|
|
|
namespace RISCVVIntrinsicsTable {
|
|
|
|
struct RISCVVIntrinsicInfo {
|
|
unsigned IntrinsicID;
|
|
uint8_t ScalarOperand;
|
|
uint8_t VLOperand;
|
|
bool hasScalarOperand() const {
|
|
// 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
|
|
return ScalarOperand != 0xF;
|
|
}
|
|
bool hasVLOperand() const {
|
|
// 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
|
|
return VLOperand != 0x1F;
|
|
}
|
|
};
|
|
|
|
using namespace RISCV;
|
|
|
|
#define GET_RISCVVIntrinsicsTable_DECL
|
|
#include "RISCVGenSearchableTables.inc"
|
|
#undef GET_RISCVVIntrinsicsTable_DECL
|
|
|
|
} // end namespace RISCVVIntrinsicsTable
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|