ca79ff07d8
Reverts llvm/llvm-project#118734 There are currently some specific versions of MSVC that are miscompiling this code (we think). We don't know why as all the other build bots and at least some folks' local Windows builds work fine. This is a candidate revert to help the relevant folks catch their builders up and have time to debug the issue. However, the expectation is to roll forward at some point with a workaround if at all possible.
271 lines
9.6 KiB
C++
271 lines
9.6 KiB
C++
//===--- Hexagon.cpp - Implement Hexagon target feature support -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements Hexagon TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "Targets.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__qdsp6__", "1");
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Builder.defineMacro("__hexagon__", "1");
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// The macro __HVXDBL__ is deprecated.
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bool DefineHvxDbl = false;
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if (CPU == "hexagonv5") {
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Builder.defineMacro("__HEXAGON_V5__");
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Builder.defineMacro("__HEXAGON_ARCH__", "5");
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if (Opts.HexagonQdsp6Compat) {
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Builder.defineMacro("__QDSP6_V5__");
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Builder.defineMacro("__QDSP6_ARCH__", "5");
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}
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} else if (CPU == "hexagonv55") {
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Builder.defineMacro("__HEXAGON_V55__");
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Builder.defineMacro("__HEXAGON_ARCH__", "55");
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Builder.defineMacro("__QDSP6_V55__");
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Builder.defineMacro("__QDSP6_ARCH__", "55");
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} else if (CPU == "hexagonv60") {
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DefineHvxDbl = true;
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Builder.defineMacro("__HEXAGON_V60__");
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Builder.defineMacro("__HEXAGON_ARCH__", "60");
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Builder.defineMacro("__QDSP6_V60__");
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Builder.defineMacro("__QDSP6_ARCH__", "60");
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} else if (CPU == "hexagonv62") {
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DefineHvxDbl = true;
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Builder.defineMacro("__HEXAGON_V62__");
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Builder.defineMacro("__HEXAGON_ARCH__", "62");
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} else if (CPU == "hexagonv65") {
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DefineHvxDbl = true;
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Builder.defineMacro("__HEXAGON_V65__");
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Builder.defineMacro("__HEXAGON_ARCH__", "65");
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} else if (CPU == "hexagonv66") {
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DefineHvxDbl = true;
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Builder.defineMacro("__HEXAGON_V66__");
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Builder.defineMacro("__HEXAGON_ARCH__", "66");
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} else if (CPU == "hexagonv67") {
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Builder.defineMacro("__HEXAGON_V67__");
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Builder.defineMacro("__HEXAGON_ARCH__", "67");
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} else if (CPU == "hexagonv67t") {
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Builder.defineMacro("__HEXAGON_V67T__");
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Builder.defineMacro("__HEXAGON_ARCH__", "67");
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} else if (CPU == "hexagonv68") {
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Builder.defineMacro("__HEXAGON_V68__");
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Builder.defineMacro("__HEXAGON_ARCH__", "68");
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} else if (CPU == "hexagonv69") {
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Builder.defineMacro("__HEXAGON_V69__");
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Builder.defineMacro("__HEXAGON_ARCH__", "69");
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} else if (CPU == "hexagonv71") {
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Builder.defineMacro("__HEXAGON_V71__");
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Builder.defineMacro("__HEXAGON_ARCH__", "71");
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} else if (CPU == "hexagonv71t") {
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Builder.defineMacro("__HEXAGON_V71T__");
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Builder.defineMacro("__HEXAGON_ARCH__", "71");
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} else if (CPU == "hexagonv73") {
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Builder.defineMacro("__HEXAGON_V73__");
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Builder.defineMacro("__HEXAGON_ARCH__", "73");
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}
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if (hasFeature("hvx-length64b")) {
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Builder.defineMacro("__HVX__");
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Builder.defineMacro("__HVX_ARCH__", HVXVersion);
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Builder.defineMacro("__HVX_LENGTH__", "64");
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}
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if (hasFeature("hvx-length128b")) {
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Builder.defineMacro("__HVX__");
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Builder.defineMacro("__HVX_ARCH__", HVXVersion);
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Builder.defineMacro("__HVX_LENGTH__", "128");
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if (DefineHvxDbl)
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Builder.defineMacro("__HVXDBL__");
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}
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if (hasFeature("audio")) {
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Builder.defineMacro("__HEXAGON_AUDIO__");
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}
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std::string NumPhySlots = isTinyCore() ? "3" : "4";
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Builder.defineMacro("__HEXAGON_PHYSICAL_SLOTS__", NumPhySlots);
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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}
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bool HexagonTargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
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if (isTinyCore())
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Features["audio"] = true;
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StringRef CPUFeature = CPU;
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CPUFeature.consume_front("hexagon");
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CPUFeature.consume_back("t");
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if (!CPUFeature.empty())
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Features[CPUFeature] = true;
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Features["long-calls"] = false;
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return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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}
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bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) {
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for (auto &F : Features) {
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if (F == "+hvx-length64b")
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HasHVX = HasHVX64B = true;
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else if (F == "+hvx-length128b")
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HasHVX = HasHVX128B = true;
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else if (F.find("+hvxv") != std::string::npos) {
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HasHVX = true;
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HVXVersion = F.substr(std::string("+hvxv").length());
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} else if (F == "-hvx")
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HasHVX = HasHVX64B = HasHVX128B = false;
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else if (F == "+long-calls")
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UseLongCalls = true;
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else if (F == "-long-calls")
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UseLongCalls = false;
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else if (F == "+audio")
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HasAudio = true;
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}
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if (CPU.compare("hexagonv68") >= 0) {
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HasLegalHalfType = true;
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HasFloat16 = true;
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}
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return true;
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}
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const char *const HexagonTargetInfo::GCCRegNames[] = {
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// Scalar registers:
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11",
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"r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
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"r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"r1:0", "r3:2", "r5:4", "r7:6", "r9:8", "r11:10", "r13:12", "r15:14",
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"r17:16", "r19:18", "r21:20", "r23:22", "r25:24", "r27:26", "r29:28",
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"r31:30",
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// Predicate registers:
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"p0", "p1", "p2", "p3",
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// Control registers:
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"c0", "c1", "c2", "c3", "c4", "c5", "c6", "c7", "c8", "c9", "c10", "c11",
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"c12", "c13", "c14", "c15", "c16", "c17", "c18", "c19", "c20", "c21",
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"c22", "c23", "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31",
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"c1:0", "c3:2", "c5:4", "c7:6", "c9:8", "c11:10", "c13:12", "c15:14",
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"c17:16", "c19:18", "c21:20", "c23:22", "c25:24", "c27:26", "c29:28",
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"c31:30",
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// Control register aliases:
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"sa0", "lc0", "sa1", "lc1", "p3:0", "m0", "m1", "usr", "pc", "ugp",
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"gp", "cs0", "cs1", "upcyclelo", "upcyclehi", "framelimit", "framekey",
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"pktcountlo", "pktcounthi", "utimerlo", "utimerhi",
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"upcycle", "pktcount", "utimer",
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// HVX vector registers:
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"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
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"v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
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"v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
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"v1:0", "v3:2", "v5:4", "v7:6", "v9:8", "v11:10", "v13:12", "v15:14",
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"v17:16", "v19:18", "v21:20", "v23:22", "v25:24", "v27:26", "v29:28",
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"v31:30",
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"v3:0", "v7:4", "v11:8", "v15:12", "v19:16", "v23:20", "v27:24", "v31:28",
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// HVX vector predicates:
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"q0", "q1", "q2", "q3",
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};
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ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const {
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return llvm::ArrayRef(GCCRegNames);
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}
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const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
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{{"sp"}, "r29"},
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{{"fp"}, "r30"},
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{{"lr"}, "r31"},
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};
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ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
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return llvm::ArrayRef(GCCRegAliases);
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}
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static constexpr Builtin::Info BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
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{#ID, TYPE, ATTRS, nullptr, HEADER, ALL_LANGUAGES},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#include "clang/Basic/BuiltinsHexagon.def"
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};
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bool HexagonTargetInfo::hasFeature(StringRef Feature) const {
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std::string VS = "hvxv" + HVXVersion;
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if (Feature == VS)
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return true;
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return llvm::StringSwitch<bool>(Feature)
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.Case("hexagon", true)
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.Case("hvx", HasHVX)
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.Case("hvx-length64b", HasHVX64B)
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.Case("hvx-length128b", HasHVX128B)
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.Case("long-calls", UseLongCalls)
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.Case("audio", HasAudio)
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.Default(false);
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}
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struct CPUSuffix {
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llvm::StringLiteral Name;
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llvm::StringLiteral Suffix;
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};
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static constexpr CPUSuffix Suffixes[] = {
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{{"hexagonv5"}, {"5"}}, {{"hexagonv55"}, {"55"}},
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{{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
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{{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
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{{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
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{{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
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{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
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{{"hexagonv73"}, {"73"}},
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};
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std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {
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StringRef Arch = Name;
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Arch.consume_front("hexagonv");
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Arch.consume_back("t");
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unsigned Val;
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if (!Arch.getAsInteger(0, Val))
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return Val;
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return std::nullopt;
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}
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const char *HexagonTargetInfo::getHexagonCPUSuffix(StringRef Name) {
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const CPUSuffix *Item = llvm::find_if(
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Suffixes, [Name](const CPUSuffix &S) { return S.Name == Name; });
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if (Item == std::end(Suffixes))
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return nullptr;
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return Item->Suffix.data();
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}
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void HexagonTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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for (const CPUSuffix &Suffix : Suffixes)
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Values.push_back(Suffix.Name);
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}
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ArrayRef<Builtin::Info> HexagonTargetInfo::getTargetBuiltins() const {
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return llvm::ArrayRef(BuiltinInfo, clang::Hexagon::LastTSBuiltin -
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Builtin::FirstTSBuiltin);
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}
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