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llvm-project/llvm/lib/Target/RISCV
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Piotr Fusik 6e7312bda6
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221) 
(and X, (C<<12|0xfff)) -> (ANDN X, ~C<<12)
    (or  X, (C<<12|0xfff)) -> (ORN  X, ~C<<12)
    (xor X, (C<<12|0xfff)) -> (XNOR X, ~C<<12)

Emits better code, typically by avoiding an `ADDI HI, -1` instruction.

Co-authored-by: Craig Topper <craig.topper@sifive.com>
2024-12-19 21:38:20 +01:00
..
AsmParser
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
2024-12-14 00:06:58 +05:30
Disassembler
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
2024-12-14 00:06:58 +05:30
GISel
[RISCV][GISel] Add legalization for more fp128 libcalls.
2024-12-16 23:39:09 -08:00
MCA
…
MCTargetDesc
[RISCV] Split OPERAND_SEW operand type for mask only instructions. (#119776)
2024-12-13 13:14:23 -08:00
TargetInfo
…
CMakeLists.txt
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
RISCV.h
[RISCV] Introduce VLOptimizer pass (#108640)
2024-10-11 09:45:35 -04:00
RISCV.td
Reland "[RISCV] Add scheduling model for mips p8700 CPU" (#120550)
2024-12-19 14:26:43 +01:00
RISCVAsmPrinter.cpp
[XRay][RISCV] RISCV support for XRay (#117368)
2024-12-10 17:57:04 -08:00
RISCVCallingConv.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVCallingConv.h
[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
2024-09-06 09:28:33 -07:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVCombine.td
[RISCV] Remove constant_fold_cast_op from RISCVPostLegalizerCombiner.
2024-11-12 23:28:48 -08:00
RISCVConstantPoolValue.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVConstantPoolValue.h
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVDeadRegisterDefinitions.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (#113981)
2024-10-28 22:37:47 -07:00
RISCVFeatures.td
[RISCV] Add NoStdExtZfa predicates to BuildPairF64Pseudo and SplitF64Pseudo.
2024-12-17 23:27:12 -08:00
RISCVFrameLowering.cpp
[llvm][RISCV] Set ScalableVector stack id in proper place (#117862)
2024-12-18 12:27:40 +03:00
RISCVFrameLowering.h
[RISCV] Add stack clash protection (#117612)
2024-12-10 16:48:26 +00:00
RISCVGatherScatterLowering.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVGISel.td
[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729)
2024-12-12 14:41:57 -08:00
RISCVIndirectBranchTracking.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVInsertWriteVXRM.cpp
[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044)
2024-11-27 13:31:39 -08:00
RISCVInstrFormats.td
[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)
2024-10-08 14:09:07 +01:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)
2024-11-11 20:59:21 -08:00
RISCVInstrInfo.cpp
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
RISCVInstrInfo.h
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
RISCVInstrInfo.td
[RISCV][GISel] Added GISelPredicateCodes to LeadingOnes*Mask (#119886)
2024-12-13 14:23:16 -08:00
RISCVInstrInfoA.td
[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC
2024-12-17 10:24:50 -08:00
RISCVInstrInfoC.td
[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)
2024-11-08 09:12:25 -08:00
RISCVInstrInfoD.td
[RISCV] Add NoStdExtZfa predicates to BuildPairF64Pseudo and SplitF64Pseudo.
2024-12-17 23:27:12 -08:00
RISCVInstrInfoF.td
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
2024-11-24 19:29:52 -08:00
RISCVInstrInfoM.td
[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)
2024-08-12 09:34:02 -07:00
RISCVInstrInfoSFB.td
[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163)
2024-10-29 21:23:31 -07:00
RISCVInstrInfoV.td
[RISCV] Mark vmvNr.v as implicitly using vtype (#118414)
2024-12-04 15:10:57 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Split OPERAND_SEW operand type for mask only instructions. (#119776)
2024-12-13 13:14:23 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787)
2024-12-12 21:11:01 -08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Use _B* suffix for vector mask logic pseudo instructions. (#119787)
2024-12-12 21:11:01 -08:00
RISCVInstrInfoXCV.td
[RISCV] Fix typo in CV_SH_rr_inc pattern (#120246)
2024-12-17 12:20:17 -08:00
RISCVInstrInfoXqci.td
[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)
2024-12-14 00:06:58 +05:30
RISCVInstrInfoXSf.td
[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274)
2024-10-30 11:52:49 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.
2024-11-19 21:41:14 -08:00
RISCVInstrInfoXVentana.td
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
RISCVInstrInfoXwch.td
…
RISCVInstrInfoZa.td
…
RISCVInstrInfoZalasr.td
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
RISCVInstrInfoZb.td
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
RISCVInstrInfoZc.td
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV] f32 roundeven pattern missed for Zfa (#118672)
2024-12-04 13:52:20 -08:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
2024-09-03 20:18:01 -07:00
RISCVInstrInfoZfh.td
[RISCV][GISel] Add register class to some isel output patterns so they can be imported.
2024-11-24 19:29:52 -08:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZimop.td
…
RISCVInstrInfoZk.td
[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)
2024-10-06 11:47:30 -07:00
RISCVInstrInfoZvfbf.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrInfoZvk.td
[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)
2024-10-31 10:21:14 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
RISCVISelDAGToDAG.h
[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
2024-12-19 21:38:20 +01:00
RISCVISelLowering.cpp
[SelectionDAG] Move SDNode::use_iterator::getOperandNo to SDUse. (#120536)
2024-12-19 09:07:42 -08:00
RISCVISelLowering.h
[RISCV] Custom legalize vp.merge for mask vectors. (#120479)
2024-12-18 19:19:14 -08:00
RISCVLandingPadSetup.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Add stack clash protection (#117612)
2024-12-10 16:48:26 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Add stack clash protection (#117612)
2024-12-10 16:48:26 +00:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
RISCVMoveMerger.cpp
…
RISCVOptWInstrs.cpp
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.
2024-12-05 16:43:30 -08:00
RISCVProcessors.td
Reland "[RISCV] Add scheduling model for mips p8700 CPU" (#120550)
2024-12-19 14:26:43 +01:00
RISCVProfiles.td
[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)
2024-11-10 07:18:05 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756)
2024-12-06 14:07:27 -05:00
RISCVRegisterInfo.h
[RISCV] Correct the precedence in isVRegClass (#116579)
2024-11-18 18:12:57 +08:00
RISCVRegisterInfo.td
[RISCV] Merge GPRPair and GPRF64Pair (#116094)
2024-11-20 10:08:55 +00:00
RISCVSchedMIPSP8700.td
Reland "[RISCV] Add scheduling model for mips p8700 CPU" (#120550)
2024-12-19 14:26:43 +01:00
RISCVSchedRocket.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSiFive7.td
[llvm][NFC] Fix typos: replace “avaliable” with “available” across various files (#114524)
2024-11-01 13:25:04 +00:00
RISCVSchedSiFiveP400.td
[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)
2024-11-21 10:59:46 -08:00
RISCVSchedSiFiveP600.td
[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)
2024-11-21 10:59:46 -08:00
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedSyntacoreSCR7.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedule.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVScheduleV.td
[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)
2024-10-28 09:37:54 -07:00
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)
2024-10-31 10:21:14 -07:00
RISCVSchedXiangShanNanHu.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
RISCVSelectionDAGInfo.h
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
RISCVSubtarget.cpp
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
RISCVSubtarget.h
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
RISCVSystemOperands.td
[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)
2024-08-21 19:23:07 -07:00
RISCVTargetMachine.cpp
[RISCV] Add software pipeliner support (#117546)
2024-12-19 13:00:08 +08:00
RISCVTargetMachine.h
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
RISCVTargetObjectFile.cpp
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVTargetObjectFile.h
[Driver] Default -msmall-data-limit= to 0 and clean up code
2024-08-19 18:20:02 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][TTI] Add llvm.fmuladd and llvm.vp.fmuladd into canSplatOperand (#119508)
2024-12-12 18:39:21 +08:00
RISCVTargetTransformInfo.h
[SLPVectorizer, TargetTransformInfo, SystemZ] Improve SLP getGatherCost(). (#112491)
2024-11-29 21:19:45 +01:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Set a barrier between mask producer and user of V0 (#114012)
2024-11-29 13:25:53 +08:00
RISCVVectorPeephole.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Set CommonVL as the largest of the users (#120349)
2024-12-19 13:22:31 -05:00
RISCVZacasABIFix.cpp
[RISCV] Remove unused includes (NFC) (#115814)
2024-11-11 22:54:54 -08:00