Piotr Fusik 6e7312bda6

[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221) ...

(and X, (C<<12|0xfff)) -> (ANDN X, ~C<<12)
    (or  X, (C<<12|0xfff)) -> (ORN  X, ~C<<12)
    (xor X, (C<<12|0xfff)) -> (XNOR X, ~C<<12)

Emits better code, typically by avoiding an `ADDI HI, -1` instruction.

Co-authored-by: Craig Topper <craig.topper@sifive.com>

2024-12-19 21:38:20 +01:00

..

AArch64

[AArch64][SVE] Use SVE for scalar FP converts in streaming[-compatible] functions (1/n) (#118505)

2024-12-19 13:16:31 +00:00

AMDGPU

[AMDGPU] Emit S_CBRANCH_SCC for floating-point conditions. (#120588)

2024-12-19 11:20:43 -08:00

ARC

[ARC,test] Change llc -march= to -mtriple=

2024-12-15 12:29:53 -08:00

ARM

[DAGCombiner] Refactor and improve ReduceLoadOpStoreWidth (#119564)

2024-12-16 12:15:11 +01:00

AVR

[AVR,test] Change llc -march= to -mtriple=

2024-12-15 10:26:33 -08:00

BPF

[BPF,test] Change llc -march= to -mtriple=

2024-12-15 11:04:24 -08:00

CSKY

…

DirectX

[DirectX][SPIRV] Consistent names for HLSL resource intrinsics (#120466)

2024-12-19 12:17:21 -07:00

Generic

[NFC][SelectionDAG] Replace generic @llvm.expect.with.probability codegen test with X86 test (#117848)

2024-12-01 17:46:08 -05:00

Hexagon

[test] Remove redundant -march= when target triple is specified in IR

2024-12-15 12:42:17 -08:00

Inputs

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Lanai

[test] Remove redundant -march= when target triple is specified in IR

2024-12-15 12:42:17 -08:00

LoongArch

[llvm][CodeGen] Intrinsic llvm.powi.* code gen for vector arguments (#118242)

2024-12-19 08:57:31 +08:00

M68k

[M68k,MSP430,test] Change llc -march= to -mtriple=

2024-12-15 10:09:30 -08:00

Mips

[test] Remove redundant -march= in llc -mtriple=

2024-12-14 17:46:30 -08:00

MIR

[AMDGPU] Make max dwords of memory cluster configurable (#119342)

2024-12-18 14:17:27 +08:00

MLRegAlloc

[MLGO] Remove extranous check lines from test input

2024-11-18 03:52:13 +00:00

MSP430

[M68k,MSP430,test] Change llc -march= to -mtriple=

2024-12-15 10:09:30 -08:00

NVPTX

[NVPTX] Avoid introducing unnecessary ProxyRegs and Movs in ISel (#120486)

2024-12-19 07:55:03 -08:00

PowerPC

[SDAG] Allow folding stack slots into sincos/frexp in more cases (#118117)

2024-12-17 10:54:17 +00:00

RISCV

[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)

2024-12-19 21:38:20 +01:00

SPARC

[Sparc,test] Change llc -march= to -mtriple=

2024-12-15 10:29:34 -08:00

SPIRV

[DirectX][SPIRV] Consistent names for HLSL resource intrinsics (#120466)

2024-12-19 12:17:21 -07:00

SystemZ

[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)

2024-12-11 17:41:19 +08:00

Thumb

Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)

2024-12-07 10:14:36 +03:00

Thumb2

[ARM] Fix BF16 lowering with FullFP16

2024-12-19 10:20:35 +00:00

VE

[VE,test] Change llc -march= to -mtriple=

2024-12-15 10:24:14 -08:00

WebAssembly

[WebAssembly] Add -i128:128 to the datalayout string. (#119204)

2024-12-10 09:21:58 -08:00

WinCFGuard

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WinEH

[WinEH] Take musttail calls into account when unlinking eh records (#119702)

2024-12-13 09:16:52 +01:00

X86

[X86] Put R20/R21/R28/R29 later in GR64 list (#120510)

2024-12-19 20:16:34 +08:00

XCore

[XCore,test] Change llc -march= to -mtriple=

2024-12-15 10:31:38 -08:00

Xtensa

[Xtensa] Implement vararg support. (#117126)

2024-12-12 03:19:31 +03:00