Luke Lau b1f4a0201a [LV] Update failing test with middle block. NFC

2024-12-18 11:51:48 +08:00

..

bf16.ll

[RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272)

2024-11-11 13:29:48 +08:00

blend-any-of-reduction-cost.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

blocks-with-dead-instructions.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

dead-ops-cost.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

defaults.ll

[VPlan] Model branch cond to enter scalar epilogue in VPlan. (#92651)

2024-07-05 10:08:42 +01:00

divrem.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

evl-compatible-loops.ll

[LV, VPlan] Check if plan is compatible to EVL transform (#92092)

2024-05-25 08:22:49 +08:00

f16.ll

[RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272)

2024-11-11 13:29:48 +08:00

first-order-recurrence-scalable-vf1.ll

[VPlan] Introduce scalar loop header in plan, remove VPLiveOut. (#109975)

2024-10-31 21:36:44 +01:00

force-vect-msg.ll

[LoopVectorize][NFC] Rewrite tests to check output of vplan cost model (#113697)

2024-11-19 08:55:39 +00:00

illegal-type.ll

[RISCV][TTI] Scale the cost of ICmp with LMUL (#88235)

2024-04-16 09:37:32 +08:00

induction-costs.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

inloop-reduction.ll

[LV][EVL] Support cast instruction with EVL-vectorization (#108351)

2024-12-11 10:01:41 +08:00

interleaved-accesses-zve32x.ll

…

interleaved-accesses.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

interleaved-cost.ll

[RISCV] Add +optimized-nfN-segment-load-store (#114414)

2024-11-04 06:43:58 +08:00

lit.local.cfg

…

lmul.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

low-trip-count.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

mask-index-type.ll

[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)

2024-12-16 11:55:48 +08:00

masked_gather_scatter.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

only-compute-cost-for-vplan-vfs.ll

[VPlan] Don't compute costs if there are no vector VPlans.

2024-06-24 08:38:31 +01:00

ordered-reduction.ll

[VPlan] Model branch cond to enter scalar epilogue in VPlan. (#92651)

2024-07-05 10:08:42 +01:00

pr87378-vpinstruction-or-drop-poison-generating-flags.ll

[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)

2024-12-16 11:55:48 +08:00

pr88802.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

reg-usage-bf16.ll

[RISCV] Add asserts requirement to loop vectorizer tests

2024-09-17 14:18:36 +08:00

reg-usage-f16.ll

[RISCV] Add asserts requirement to loop vectorizer tests

2024-09-17 14:18:36 +08:00

reg-usage.ll

…

riscv-interleaved.ll

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06 11:53:33 +00:00

riscv-unroll.ll

…

riscv-vector-reverse.ll

[VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (#114292)

2024-12-12 15:58:16 +00:00

safe-dep-distance.ll

…

scalable-basics.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

scalable-reductions.ll

[RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272)

2024-11-11 13:29:48 +08:00

scalable-tailfold.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

scalable-vf-hint.ll

…

select-cmp-reduction.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

select-invariant-cond-cost.ll

[VPlan] Also check if plan for best legacy VF contains simplifications.

2024-11-08 20:53:03 +00:00

short-trip-count.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

strided-accesses.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

truncate-to-minimal-bitwidth-cost.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

truncate-to-minimal-bitwidth-evl-crash.ll

[VPlan] Handle VPWidenCastRecipe without underlying value in EVL transform (#120194)

2024-12-18 11:28:07 +08:00

type-info-cache-evl-crash.ll

[LV] Update failing test with middle block. NFC

2024-12-18 11:51:48 +08:00

uniform-load-store.ll

[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)

2024-12-16 11:55:48 +08:00

unroll-in-loop-vectorizer.ll

…

veclib-function-calls.ll

[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)

2024-11-26 12:25:54 +03:00

vectorize-force-tail-with-evl-bin-unary-ops-args.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

vectorize-force-tail-with-evl-call-intrinsics.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

vectorize-force-tail-with-evl-cast-intrinsics.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

vectorize-force-tail-with-evl-cond-reduction.ll

[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)

2024-12-16 11:55:48 +08:00

vectorize-force-tail-with-evl-gather-scatter.ll

[LV, VPlan] Check if plan is compatible to EVL transform (#92092)

2024-05-25 08:22:49 +08:00

vectorize-force-tail-with-evl-inloop-reduction.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

vectorize-force-tail-with-evl-interleave.ll

[VPlan] Omit zero add in VPWidenIntOrFpInductionRecipe (#119668)

2024-12-16 11:55:48 +08:00

vectorize-force-tail-with-evl-intermediate-store.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

vectorize-force-tail-with-evl-iv32.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

vectorize-force-tail-with-evl-known-no-overflow.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

vectorize-force-tail-with-evl-masked-loadstore.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

vectorize-force-tail-with-evl-no-masking.ll

…

vectorize-force-tail-with-evl-ordered-reduction.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

vectorize-force-tail-with-evl-reduction-cost.ll

[LV] Add missing REQUIRES: asserts to test

2024-11-14 17:41:40 +09:00

vectorize-force-tail-with-evl-reduction.ll

[LV][EVL] Support call instruction with EVL-vectorization (#110412)

2024-11-28 10:05:08 +08:00

vectorize-force-tail-with-evl-reverse-load-store.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

vectorize-force-tail-with-evl-safe-dep-distance.ll

[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)

2024-11-28 10:12:41 +00:00

vectorize-force-tail-with-evl-uniform-store.ll

[VPlan] Support VPReverseVectorPointer in DataWithEVL vectorization (#113667)

2024-11-22 17:18:39 +08:00

vectorize-vp-intrinsics.ll

[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. (#116856)

2024-11-21 11:21:12 +00:00

vf-will-not-generate-any-vector-insts.ll

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17 20:44:32 +00:00

vplan-vp-call-intrinsics.ll

[LV][EVL] Support cast instruction with EVL-vectorization (#108351)

2024-12-11 10:01:41 +08:00

vplan-vp-cast-intrinsics.ll

[Test] Fix the failed test of #108351 (#119495)

2024-12-11 11:43:25 +08:00

vplan-vp-intrinsics-reduction.ll

[VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (#114292)

2024-12-12 15:58:16 +00:00

vplan-vp-intrinsics.ll

[VPlan] Use VPInstruction::Name when assigning names (NFCI).

2024-10-18 05:52:35 +01:00

vplan-vp-select-intrinsics.ll

[VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (#114292)

2024-12-12 15:58:16 +00:00

zvl32b.ll

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00