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llvm-project/llvm/test/CodeGen/MIR/AMDGPU
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Mirko Brkusanin 8b08fa0103 Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access" 
This reverts commit f5cd7ec9f3fc969ff5e1feed961996844333de3b.

Certain rocPRIM/rocThrust/hipCUB tests were failing because of this change.
2020-09-29 15:33:34 +02:00
..
expected-target-index-name.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
intrinsics.mir
…
invalid-target-index-operand.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
lit.local.cfg
…
llc-target-cpu-attr-from-cmdline-ir.mir
Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"
2020-09-29 15:33:34 +02:00
llc-target-cpu-attr-from-cmdline.mir
Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"
2020-09-29 15:33:34 +02:00
load-store-opt-dlc.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
machine-function-info-dynlds-align-invalid-case.mir
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
machine-function-info-no-ir.mir
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
machine-function-info-register-parse-error1.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
machine-function-info-register-parse-error2.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
machine-function-info.ll
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
mfi-frame-offset-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-frame-offset-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-scratch-rsrc-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-parse-error-stack-ptr-offset-reg.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-scratch-rsrc-reg-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mfi-stack-ptr-offset-reg-class.mir
[AMDGPU] Avoid hard-coded line numbers in error message checks
2020-04-23 21:06:09 +01:00
mir-canon-multi.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
mircanon-memoperands.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
parse-order-reserved-regs.mir
[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)
2020-09-03 16:13:09 -04:00
stack-id.mir
…
subreg-def-is-not-ssa.mir
MIR: Infer not-SSA for subregister defs
2020-08-27 16:56:16 -04:00
syncscopes.mir
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target-flags.mir
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
target-index-operands.mir
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00