f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-none-eabi -o - | FileCheck %s
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define zeroext i1 @bigger(ptr nocapture readonly %c, ptr nocapture readonly %e, i64 %d, i64 %p1) {
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; CHECK-LABEL: bigger:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andb $7, %cl
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; CHECK-NEXT: movb $8, %al
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; CHECK-NEXT: subb %cl, %al
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; CHECK-NEXT: movl $5, %r8d
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shll %cl, %r8d
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; CHECK-NEXT: movzbl (%rsi,%rdx), %eax
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; CHECK-NEXT: xorb (%rdi,%rdx), %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: andl %r8d, %eax
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; CHECK-NEXT: testb $-1, %al
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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entry:
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%0 = trunc i64 %p1 to i16
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%1 = and i16 %0, 7
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%sh_prom = sub nuw nsw i16 8, %1
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%shl = shl nuw nsw i16 5, %sh_prom
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%arrayidx = getelementptr inbounds i8, ptr %c, i64 %d
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%2 = load i8, ptr %arrayidx, align 1
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%3 = and i16 %shl, 255
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%conv2 = zext i16 %3 to i32
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%arrayidx3 = getelementptr inbounds i8, ptr %e, i64 %d
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%4 = load i8, ptr %arrayidx3, align 1
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%5 = xor i8 %4, %2
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%6 = zext i8 %5 to i32
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%7 = and i32 %6, %conv2
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%cmp.not = icmp eq i32 %7, 0
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ret i1 %cmp.not
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}
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