6b54c92be0
This is a generalization of the LookupPtrRegClass mechanism. AMDGPU has several use cases for swapping the register class of instruction operands based on the subtarget, but none of them really fit into the box of being pointer-like. The current system requires manual management of an arbitrary integer ID. For the AMDGPU use case, this would end up being around 40 new entries to manage. This just introduces the base infrastructure. I have ports of all the target specific usage of PointerLikeRegClass ready.
439 lines
16 KiB
C++
439 lines
16 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "InstructionEncoding.h"
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#include "CodeGenInstruction.h"
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#include "VarLenCodeEmitterGen.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "llvm/TableGen/Error.h"
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using namespace llvm;
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std::pair<std::string, bool>
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InstructionEncoding::findOperandDecoderMethod(const CodeGenTarget &Target,
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const Record *Record) {
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std::string Decoder;
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const RecordVal *DecoderString = Record->getValue("DecoderMethod");
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const StringInit *String =
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DecoderString ? dyn_cast<StringInit>(DecoderString->getValue()) : nullptr;
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if (String) {
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Decoder = String->getValue().str();
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if (!Decoder.empty())
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return {Decoder, false};
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}
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if (Record->isSubClassOf("RegisterOperand"))
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// Allows use of a DecoderMethod in referenced RegisterClass if set.
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return findOperandDecoderMethod(Target, Record->getValueAsDef("RegClass"));
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if (Record->isSubClassOf("RegisterClass")) {
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Decoder = "Decode" + Record->getName().str() + "RegisterClass";
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} else if (Record->isSubClassOf("RegClassByHwMode")) {
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Decoder = "Decode" + Record->getName().str() + "RegClassByHwMode";
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} else if (Record->isSubClassOf("PointerLikeRegClass")) {
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Decoder = "DecodePointerLikeRegClass" +
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utostr(Record->getValueAsInt("RegClassKind"));
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}
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return {Decoder, true};
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}
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OperandInfo InstructionEncoding::getOpInfo(const CodeGenTarget &Target,
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const Record *TypeRecord) {
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const RecordVal *HasCompleteDecoderVal =
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TypeRecord->getValue("hasCompleteDecoder");
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const BitInit *HasCompleteDecoderBit =
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HasCompleteDecoderVal
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? dyn_cast<BitInit>(HasCompleteDecoderVal->getValue())
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: nullptr;
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bool HasCompleteDecoder =
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HasCompleteDecoderBit ? HasCompleteDecoderBit->getValue() : true;
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return OperandInfo(findOperandDecoderMethod(Target, TypeRecord).first,
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HasCompleteDecoder);
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}
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void InstructionEncoding::parseVarLenEncoding(const VarLenInst &VLI) {
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InstBits = KnownBits(VLI.size());
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SoftFailMask = APInt(VLI.size(), 0);
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// Parse Inst field.
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unsigned I = 0;
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for (const EncodingSegment &S : VLI) {
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if (const auto *SegmentBits = dyn_cast<BitsInit>(S.Value)) {
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for (const Init *V : SegmentBits->getBits()) {
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if (const auto *B = dyn_cast<BitInit>(V)) {
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if (B->getValue())
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InstBits.One.setBit(I);
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else
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InstBits.Zero.setBit(I);
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}
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++I;
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}
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} else if (const auto *B = dyn_cast<BitInit>(S.Value)) {
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if (B->getValue())
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InstBits.One.setBit(I);
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else
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InstBits.Zero.setBit(I);
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++I;
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} else {
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I += S.BitWidth;
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}
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}
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assert(I == VLI.size());
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}
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void InstructionEncoding::parseFixedLenEncoding(
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const BitsInit &RecordInstBits) {
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// For fixed length instructions, sometimes the `Inst` field specifies more
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// bits than the actual size of the instruction, which is specified in `Size`.
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// In such cases, we do some basic validation and drop the upper bits.
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unsigned BitWidth = EncodingDef->getValueAsInt("Size") * 8;
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unsigned InstNumBits = RecordInstBits.getNumBits();
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// Returns true if all bits in `Bits` are zero or unset.
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auto CheckAllZeroOrUnset = [&](ArrayRef<const Init *> Bits,
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const RecordVal *Field) {
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bool AllZeroOrUnset = llvm::all_of(Bits, [](const Init *Bit) {
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if (const auto *BI = dyn_cast<BitInit>(Bit))
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return !BI->getValue();
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return isa<UnsetInit>(Bit);
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});
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if (AllZeroOrUnset)
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return;
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PrintNote([Field](raw_ostream &OS) { Field->print(OS); });
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PrintFatalError(EncodingDef, Twine(Name) + ": Size is " + Twine(BitWidth) +
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" bits, but " + Field->getName() +
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" bits beyond that are not zero/unset");
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};
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if (InstNumBits < BitWidth)
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PrintFatalError(EncodingDef, Twine(Name) + ": Size is " + Twine(BitWidth) +
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" bits, but Inst specifies only " +
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Twine(InstNumBits) + " bits");
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if (InstNumBits > BitWidth) {
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// Ensure that all the bits beyond 'Size' are 0 or unset (i.e., carry no
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// actual encoding).
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ArrayRef<const Init *> UpperBits =
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RecordInstBits.getBits().drop_front(BitWidth);
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const RecordVal *InstField = EncodingDef->getValue("Inst");
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CheckAllZeroOrUnset(UpperBits, InstField);
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}
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ArrayRef<const Init *> ActiveInstBits =
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RecordInstBits.getBits().take_front(BitWidth);
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InstBits = KnownBits(BitWidth);
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SoftFailMask = APInt(BitWidth, 0);
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// Parse Inst field.
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for (auto [I, V] : enumerate(ActiveInstBits)) {
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if (const auto *B = dyn_cast<BitInit>(V)) {
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if (B->getValue())
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InstBits.One.setBit(I);
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else
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InstBits.Zero.setBit(I);
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}
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}
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// Parse SoftFail field.
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const RecordVal *SoftFailField = EncodingDef->getValue("SoftFail");
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if (!SoftFailField)
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return;
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const auto *SFBits = dyn_cast<BitsInit>(SoftFailField->getValue());
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if (!SFBits || SFBits->getNumBits() != InstNumBits) {
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PrintNote(EncodingDef->getLoc(), "in record");
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PrintFatalError(SoftFailField,
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formatv("SoftFail field, if defined, must be "
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"of the same type as Inst, which is bits<{}>",
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InstNumBits));
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}
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if (InstNumBits > BitWidth) {
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// Ensure that all upper bits of `SoftFail` are 0 or unset.
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ArrayRef<const Init *> UpperBits = SFBits->getBits().drop_front(BitWidth);
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CheckAllZeroOrUnset(UpperBits, SoftFailField);
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}
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ArrayRef<const Init *> ActiveSFBits = SFBits->getBits().take_front(BitWidth);
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for (auto [I, V] : enumerate(ActiveSFBits)) {
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if (const auto *B = dyn_cast<BitInit>(V); B && B->getValue()) {
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if (!InstBits.Zero[I] && !InstBits.One[I]) {
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PrintNote(EncodingDef->getLoc(), "in record");
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PrintError(SoftFailField,
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formatv("SoftFail{{{0}} = 1 requires Inst{{{0}} "
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"to be fully defined (0 or 1, not '?')",
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I));
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}
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SoftFailMask.setBit(I);
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}
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}
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}
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void InstructionEncoding::parseVarLenOperands(const CodeGenTarget &Target,
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const VarLenInst &VLI) {
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SmallVector<int> TiedTo;
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for (const auto &[Idx, Op] : enumerate(Inst->Operands)) {
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if (Op.MIOperandInfo && Op.MIOperandInfo->getNumArgs() > 0)
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for (auto *Arg : Op.MIOperandInfo->getArgs())
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Operands.push_back(getOpInfo(Target, cast<DefInit>(Arg)->getDef()));
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else
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Operands.push_back(getOpInfo(Target, Op.Rec));
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int TiedReg = Op.getTiedRegister();
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TiedTo.push_back(-1);
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if (TiedReg != -1) {
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TiedTo[Idx] = TiedReg;
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TiedTo[TiedReg] = Idx;
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}
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}
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unsigned CurrBitPos = 0;
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for (const auto &EncodingSegment : VLI) {
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unsigned Offset = 0;
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StringRef OpName;
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if (const StringInit *SI = dyn_cast<StringInit>(EncodingSegment.Value)) {
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OpName = SI->getValue();
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} else if (const DagInit *DI = dyn_cast<DagInit>(EncodingSegment.Value)) {
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OpName = cast<StringInit>(DI->getArg(0))->getValue();
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Offset = cast<IntInit>(DI->getArg(2))->getValue();
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}
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if (!OpName.empty()) {
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auto OpSubOpPair = Inst->Operands.parseOperandName(OpName);
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unsigned OpIdx = Inst->Operands.getFlattenedOperandNumber(OpSubOpPair);
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Operands[OpIdx].addField(CurrBitPos, EncodingSegment.BitWidth, Offset);
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if (!EncodingSegment.CustomDecoder.empty())
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Operands[OpIdx].Decoder = EncodingSegment.CustomDecoder.str();
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int TiedReg = TiedTo[OpSubOpPair.first];
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if (TiedReg != -1) {
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unsigned OpIdx = Inst->Operands.getFlattenedOperandNumber(
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{TiedReg, OpSubOpPair.second});
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Operands[OpIdx].addField(CurrBitPos, EncodingSegment.BitWidth, Offset);
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}
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}
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CurrBitPos += EncodingSegment.BitWidth;
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}
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}
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static void debugDumpRecord(const Record &Rec) {
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// Dump the record, so we can see what's going on.
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PrintNote([&Rec](raw_ostream &OS) {
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OS << "Dumping record for previous error:\n";
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OS << Rec;
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});
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}
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/// For an operand field named OpName: populate OpInfo.InitValue with the
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/// constant-valued bit values, and OpInfo.Fields with the ranges of bits to
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/// insert from the decoded instruction.
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static void addOneOperandFields(const Record *EncodingDef,
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const BitsInit &InstBits,
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std::map<StringRef, StringRef> &TiedNames,
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const Record *OpRec, StringRef OpName,
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OperandInfo &OpInfo) {
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OpInfo.Name = OpName;
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// Find a field with the operand's name.
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const RecordVal *OpEncodingField = EncodingDef->getValue(OpName);
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// If there is no such field, try tied operand's name.
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if (!OpEncodingField) {
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if (auto I = TiedNames.find(OpName); I != TiedNames.end())
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OpEncodingField = EncodingDef->getValue(I->second);
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// If still no luck, we're done with this operand.
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if (!OpEncodingField) {
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OpInfo.HasNoEncoding = true;
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return;
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}
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}
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// Some or all bits of the operand may be required to be 0 or 1 depending
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// on the instruction's encoding. Collect those bits.
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if (const auto *OpBit = dyn_cast<BitInit>(OpEncodingField->getValue())) {
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OpInfo.InitValue = OpBit->getValue();
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return;
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}
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if (const auto *OpBits = dyn_cast<BitsInit>(OpEncodingField->getValue())) {
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if (OpBits->getNumBits() == 0) {
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if (OpInfo.Decoder.empty()) {
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PrintError(EncodingDef->getLoc(), "operand '" + OpName + "' of type '" +
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OpRec->getName() +
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"' must have a decoder method");
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}
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return;
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}
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for (unsigned I = 0; I < OpBits->getNumBits(); ++I) {
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if (const auto *OpBit = dyn_cast<BitInit>(OpBits->getBit(I)))
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OpInfo.InitValue = OpInfo.InitValue.value_or(0) |
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static_cast<uint64_t>(OpBit->getValue()) << I;
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}
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}
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// Find out where the variable bits of the operand are encoded. The bits don't
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// have to be consecutive or in ascending order. For example, an operand could
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// be encoded as follows:
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//
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// 7 6 5 4 3 2 1 0
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// {1, op{5}, op{2}, op{1}, 0, op{4}, op{3}, ?}
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//
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// In this example the operand is encoded in three segments:
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//
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// Base Width Offset
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// op{2...1} 4 2 1
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// op{4...3} 1 2 3
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// op{5} 6 1 5
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//
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for (unsigned I = 0, J = 0; I != InstBits.getNumBits(); I = J) {
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const VarInit *Var;
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unsigned Offset = 0;
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for (; J != InstBits.getNumBits(); ++J) {
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const Init *BitJ = InstBits.getBit(J);
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if (const auto *VBI = dyn_cast<VarBitInit>(BitJ)) {
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Var = dyn_cast<VarInit>(VBI->getBitVar());
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if (I == J)
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Offset = VBI->getBitNum();
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else if (VBI->getBitNum() != Offset + J - I)
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break;
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} else {
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Var = dyn_cast<VarInit>(BitJ);
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}
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if (!Var ||
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(Var->getName() != OpName && Var->getName() != TiedNames[OpName]))
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break;
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}
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if (I == J)
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++J;
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else
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OpInfo.addField(I, J - I, Offset);
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}
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}
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void InstructionEncoding::parseFixedLenOperands(const CodeGenTarget &Target,
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const BitsInit &Bits) {
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// Search for tied operands, so that we can correctly instantiate
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// operands that are not explicitly represented in the encoding.
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std::map<StringRef, StringRef> TiedNames;
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for (const auto &Op : Inst->Operands) {
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for (const auto &[J, CI] : enumerate(Op.Constraints)) {
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if (!CI.isTied())
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continue;
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std::pair<unsigned, unsigned> SO =
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Inst->Operands.getSubOperandNumber(CI.getTiedOperand());
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StringRef TiedName = Inst->Operands[SO.first].SubOpNames[SO.second];
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if (TiedName.empty())
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TiedName = Inst->Operands[SO.first].Name;
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StringRef MyName = Op.SubOpNames[J];
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if (MyName.empty())
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MyName = Op.Name;
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TiedNames[MyName] = TiedName;
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TiedNames[TiedName] = MyName;
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}
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}
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// For each operand, see if we can figure out where it is encoded.
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for (const CGIOperandList::OperandInfo &Op : Inst->Operands) {
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// Lookup the decoder method and construct a new OperandInfo to hold our
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// result.
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OperandInfo OpInfo = getOpInfo(Target, Op.Rec);
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// If we have named sub-operands...
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if (Op.MIOperandInfo && !Op.SubOpNames[0].empty()) {
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// Then there should not be a custom decoder specified on the top-level
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// type.
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if (!OpInfo.Decoder.empty()) {
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PrintError(EncodingDef,
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"DecoderEmitter: operand \"" + Op.Name + "\" has type \"" +
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Op.Rec->getName() +
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"\" with a custom DecoderMethod, but also named "
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"sub-operands.");
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continue;
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}
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// Decode each of the sub-ops separately.
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for (auto [SubOpName, SubOp] :
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zip_equal(Op.SubOpNames, Op.MIOperandInfo->getArgs())) {
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const Record *SubOpRec = cast<DefInit>(SubOp)->getDef();
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OperandInfo SubOpInfo = getOpInfo(Target, SubOpRec);
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addOneOperandFields(EncodingDef, Bits, TiedNames, SubOpRec, SubOpName,
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SubOpInfo);
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Operands.push_back(std::move(SubOpInfo));
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}
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continue;
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}
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// Otherwise, if we have an operand with sub-operands, but they aren't
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// named...
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if (Op.MIOperandInfo && OpInfo.Decoder.empty()) {
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// If we have sub-ops, we'd better have a custom decoder.
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// (Otherwise we don't know how to populate them properly...)
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if (Op.MIOperandInfo->getNumArgs()) {
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PrintError(EncodingDef,
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"DecoderEmitter: operand \"" + Op.Name +
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"\" has non-empty MIOperandInfo, but doesn't "
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"have a custom decoder!");
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debugDumpRecord(*EncodingDef);
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continue;
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}
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}
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addOneOperandFields(EncodingDef, Bits, TiedNames, Op.Rec, Op.Name, OpInfo);
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Operands.push_back(std::move(OpInfo));
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}
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}
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InstructionEncoding::InstructionEncoding(const CodeGenTarget &Target,
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const Record *EncodingDef,
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const CodeGenInstruction *Inst)
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: EncodingDef(EncodingDef), Inst(Inst) {
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const Record *InstDef = Inst->TheDef;
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// Give this encoding a name.
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if (EncodingDef != InstDef)
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Name = (EncodingDef->getName() + Twine(':')).str();
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Name.append(InstDef->getName());
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DecoderNamespace = EncodingDef->getValueAsString("DecoderNamespace");
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DecoderMethod = EncodingDef->getValueAsString("DecoderMethod");
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if (!DecoderMethod.empty())
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HasCompleteDecoder = EncodingDef->getValueAsBit("hasCompleteDecoder");
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const RecordVal *InstField = EncodingDef->getValue("Inst");
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if (const auto *DI = dyn_cast<DagInit>(InstField->getValue())) {
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VarLenInst VLI(DI, InstField);
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parseVarLenEncoding(VLI);
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// If the encoding has a custom decoder, don't bother parsing the operands.
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if (DecoderMethod.empty())
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parseVarLenOperands(Target, VLI);
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} else {
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const auto *BI = cast<BitsInit>(InstField->getValue());
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parseFixedLenEncoding(*BI);
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// If the encoding has a custom decoder, don't bother parsing the operands.
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if (DecoderMethod.empty())
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parseFixedLenOperands(Target, *BI);
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}
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if (DecoderMethod.empty()) {
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// A generated decoder is always successful if none of the operand
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// decoders can fail (all are always successful).
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HasCompleteDecoder = all_of(Operands, [](const OperandInfo &Op) {
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// By default, a generated operand decoder is assumed to always succeed.
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// This can be overridden by the user.
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return Op.Decoder.empty() || Op.HasCompleteDecoder;
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});
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}
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}
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