Vikram S. Adve 7366fa1aa6 (1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341
2003-05-27 00:05:23 +00:00
..
2003-04-23 16:36:11 +00:00
2003-05-09 03:27:41 +00:00
2003-04-23 16:36:11 +00:00
2003-01-15 19:48:13 +00:00