Daniel Sanders c171f65a87 [mips] Add cache and pref instructions ...

Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

llvm-svn: 210900

2014-06-13 13:15:59 +00:00

..

CMakeLists.txt

Cleaning up a bunch of pre-Visual C++ 2012 build hacks.

2014-03-04 09:23:33 +00:00

LLVMBuild.txt

LLVMBuild.txt: Reformat.

2014-04-10 11:16:17 +00:00

Makefile

This is a resubmittal. For some reason it broke the bots yesterday

2013-01-19 02:00:40 +00:00

MipsDisassembler.cpp

[mips] Add cache and pref instructions

2014-06-13 13:15:59 +00:00