fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
383 lines
14 KiB
LLVM
383 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=SI,FUNC,GFX7 %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=SI,FUNC,GFX8 %s
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; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
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; the global address space(1) uses 64-bit pointers. These tests check to make sure
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; the correct pointer size is used for the local address space.
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; The e{{32|64}} suffix on the instructions refers to the encoding size and not
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; the size of the operands. The operand size is denoted in the instruction name.
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; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
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; instructions with B64, U64, and I64 take 64-bit operands.
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define amdgpu_kernel void @local_address_load(ptr addrspace(1) %out, ptr addrspace(3) %in) {
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; GFX7-LABEL: local_address_load:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0xb
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: ds_read_b32 v0, v0
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: local_address_load:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: ds_read_b32 v0, v0
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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entry:
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%0 = load i32, ptr addrspace(3) %in
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store i32 %0, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @local_address_gep(ptr addrspace(1) %out, ptr addrspace(3) %in, i32 %offset) {
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; GFX7-LABEL: local_address_gep:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_lshl_b32 s3, s3, 2
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; GFX7-NEXT: s_add_i32 s2, s2, s3
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: ds_read_b32 v0, v0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: local_address_gep:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_lshl_b32 s3, s3, 2
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; GFX8-NEXT: s_add_i32 s2, s2, s3
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: ds_read_b32 v0, v0
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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entry:
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%0 = getelementptr i32, ptr addrspace(3) %in, i32 %offset
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%1 = load i32, ptr addrspace(3) %0
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store i32 %1, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @local_address_gep_const_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) {
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; GFX7-LABEL: local_address_gep_const_offset:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0xb
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: ds_read_b32 v0, v0 offset:4
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: local_address_gep_const_offset:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: ds_read_b32 v0, v0 offset:4
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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entry:
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%0 = getelementptr i32, ptr addrspace(3) %in, i32 1
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%1 = load i32, ptr addrspace(3) %0
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store i32 %1, ptr addrspace(1) %out
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ret void
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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define amdgpu_kernel void @local_address_gep_large_const_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) {
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; GFX7-LABEL: local_address_gep_large_const_offset:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0xb
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_add_i32 s2, s2, 0x10004
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: ds_read_b32 v0, v0
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: local_address_gep_large_const_offset:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_add_i32 s2, s2, 0x10004
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: ds_read_b32 v0, v0
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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entry:
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%0 = getelementptr i32, ptr addrspace(3) %in, i32 16385
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%1 = load i32, ptr addrspace(3) %0
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store i32 %1, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @null_32bit_lds_ptr(ptr addrspace(1) %out, ptr addrspace(3) %lds) nounwind {
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; GFX7-LABEL: null_32bit_lds_ptr:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_load_dword s6, s[4:5], 0xb
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: s_movk_i32 s4, 0x7b
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_cmp_lg_u32 s6, 0
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; GFX7-NEXT: s_cselect_b32 s4, s4, 0x1c8
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; GFX7-NEXT: v_mov_b32_e32 v0, s4
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: null_32bit_lds_ptr:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dword s6, s[4:5], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_movk_i32 s4, 0x7b
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_cmp_lg_u32 s6, 0
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; GFX8-NEXT: s_cselect_b32 s4, s4, 0x1c8
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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%cmp = icmp ne ptr addrspace(3) %lds, null
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%x = select i1 %cmp, i32 123, i32 456
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store i32 %x, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @mul_32bit_ptr(ptr addrspace(1) %out, ptr addrspace(3) %lds, i32 %tid) {
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; GFX7-LABEL: mul_32bit_ptr:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_mul_i32 s3, s3, 12
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; GFX7-NEXT: s_add_i32 s2, s2, s3
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: ds_read_b32 v0, v0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: mul_32bit_ptr:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_mul_i32 s3, s3, 12
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; GFX8-NEXT: s_add_i32 s2, s2, s3
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: ds_read_b32 v0, v0
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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%ptr = getelementptr [3 x float], ptr addrspace(3) %lds, i32 %tid, i32 0
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%val = load float, ptr addrspace(3) %ptr
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store float %val, ptr addrspace(1) %out
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ret void
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}
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@g_lds = addrspace(3) global float poison, align 4
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define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %out, i32 %tid) {
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; GFX7-LABEL: infer_ptr_alignment_global_offset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: v_mov_b32_e32 v0, 0
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: ds_read_b32 v0, v0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: infer_ptr_alignment_global_offset:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: v_mov_b32_e32 v0, 0
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: ds_read_b32 v0, v0
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; GFX8-NEXT: s_mov_b32 s3, 0xf000
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; GFX8-NEXT: s_mov_b32 s2, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX8-NEXT: s_endpgm
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%val = load float, ptr addrspace(3) @g_lds
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store float %val, ptr addrspace(1) %out
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ret void
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}
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@ptr = addrspace(3) global ptr addrspace(3) poison
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@dst = addrspace(3) global [16383 x i32] poison
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define amdgpu_kernel void @global_ptr() nounwind {
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; SI-LABEL: global_ptr:
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; SI: ; %bb.0:
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; SI-NEXT: v_mov_b32_e32 v0, 64
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_mov_b32 m0, -1
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; SI-NEXT: ds_write_b32 v1, v0 offset:65532
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; SI-NEXT: s_endpgm
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store ptr addrspace(3) getelementptr ([16383 x i32], ptr addrspace(3) @dst, i32 0, i32 16), ptr addrspace(3) @ptr
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ret void
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}
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define amdgpu_kernel void @local_address_store(ptr addrspace(3) %out, i32 %val) {
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; GFX7-LABEL: local_address_store:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s0
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; GFX7-NEXT: v_mov_b32_e32 v1, s1
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; GFX7-NEXT: ds_write_b32 v0, v1
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: local_address_store:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: ds_write_b32 v0, v1
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; GFX8-NEXT: s_endpgm
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store i32 %val, ptr addrspace(3) %out
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ret void
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}
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define amdgpu_kernel void @local_address_gep_store(ptr addrspace(3) %out, i32, i32 %val, i32 %offset) {
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; GFX7-LABEL: local_address_gep_store:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 m0, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_lshl_b32 s1, s1, 2
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; GFX7-NEXT: v_mov_b32_e32 v0, s0
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; GFX7-NEXT: s_add_i32 s0, s2, s1
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; GFX7-NEXT: v_mov_b32_e32 v1, s0
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; GFX7-NEXT: ds_write_b32 v1, v0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: local_address_gep_store:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
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; GFX8-NEXT: s_load_dword s2, s[4:5], 0x24
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; GFX8-NEXT: s_mov_b32 m0, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_lshl_b32 s1, s1, 2
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: s_add_i32 s0, s2, s1
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; GFX8-NEXT: v_mov_b32_e32 v1, s0
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; GFX8-NEXT: ds_write_b32 v1, v0
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|
; GFX8-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(3) %out, i32 %offset
|
|
store i32 %val, ptr addrspace(3) %gep, align 4
|
|
ret void
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|
}
|
|
|
|
define amdgpu_kernel void @local_address_gep_const_offset_store(ptr addrspace(3) %out, i32 %val) {
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|
; GFX7-LABEL: local_address_gep_const_offset_store:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
|
; GFX7-NEXT: s_mov_b32 m0, -1
|
|
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX7-NEXT: ds_write_b32 v0, v1 offset:4
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: local_address_gep_const_offset_store:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: s_mov_b32 m0, -1
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: ds_write_b32 v0, v1 offset:4
|
|
; GFX8-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(3) %out, i32 1
|
|
store i32 %val, ptr addrspace(3) %gep, align 4
|
|
ret void
|
|
}
|
|
|
|
; Offset too large, can't fold into 16-bit immediate offset.
|
|
define amdgpu_kernel void @local_address_gep_large_const_offset_store(ptr addrspace(3) %out, i32 %val) {
|
|
; GFX7-LABEL: local_address_gep_large_const_offset_store:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
|
|
; GFX7-NEXT: s_mov_b32 m0, -1
|
|
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX7-NEXT: s_add_i32 s0, s0, 0x10004
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, s1
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s0
|
|
; GFX7-NEXT: ds_write_b32 v1, v0
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX8-LABEL: local_address_gep_large_const_offset_store:
|
|
; GFX8: ; %bb.0:
|
|
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: s_mov_b32 m0, -1
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: s_add_i32 s0, s0, 0x10004
|
|
; GFX8-NEXT: v_mov_b32_e32 v0, s1
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s0
|
|
; GFX8-NEXT: ds_write_b32 v1, v0
|
|
; GFX8-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(3) %out, i32 16385
|
|
store i32 %val, ptr addrspace(3) %gep, align 4
|
|
ret void
|
|
}
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; FUNC: {{.*}}
|