fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
114 lines
4.3 KiB
LLVM
114 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @test_i128_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {
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; GCN-LABEL: test_i128_vreg:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
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; GCN-NEXT: s_mov_b32 s11, 0xf000
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; GCN-NEXT: s_mov_b32 s14, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: s_mov_b32 s15, s11
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; GCN-NEXT: s_mov_b64 s[6:7], s[14:15]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[12:13], s[2:3]
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; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[12:15], 0 addr64
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; GCN-NEXT: buffer_load_dwordx4 v[4:7], v[4:5], s[4:7], 0 addr64
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; GCN-NEXT: s_mov_b32 s10, -1
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; GCN-NEXT: s_mov_b32 s8, s0
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; GCN-NEXT: s_mov_b32 s9, s1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
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; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v6, vcc
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; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr i128, ptr addrspace(1) %inA, i32 %tid
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%b_ptr = getelementptr i128, ptr addrspace(1) %inB, i32 %tid
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%a = load i128, ptr addrspace(1) %a_ptr
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%b = load i128, ptr addrspace(1) %b_ptr
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%result = add i128 %a, %b
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store i128 %result, ptr addrspace(1) %out
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ret void
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}
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; Check that the SGPR add operand is correctly moved to a VGPR.
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define amdgpu_kernel void @sgpr_operand(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i128 %a) {
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; GCN-LABEL: sgpr_operand:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_add_u32 s4, s8, s4
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; GCN-NEXT: s_addc_u32 s5, s9, s5
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; GCN-NEXT: s_addc_u32 s6, s10, s6
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; GCN-NEXT: s_addc_u32 s7, s11, s7
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: v_mov_b32_e32 v2, s6
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; GCN-NEXT: v_mov_b32_e32 v3, s7
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%foo = load i128, ptr addrspace(1) %in, align 8
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%result = add i128 %foo, %a
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store i128 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @sgpr_operand_reversed(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i128 %a) {
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; GCN-LABEL: sgpr_operand_reversed:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_add_u32 s4, s4, s8
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; GCN-NEXT: s_addc_u32 s5, s5, s9
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; GCN-NEXT: s_addc_u32 s6, s6, s10
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; GCN-NEXT: s_addc_u32 s7, s7, s11
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: v_mov_b32_e32 v2, s6
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; GCN-NEXT: v_mov_b32_e32 v3, s7
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%foo = load i128, ptr addrspace(1) %in, align 8
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%result = add i128 %a, %foo
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store i128 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @test_sreg(ptr addrspace(1) noalias %out, i128 %a, i128 %b) {
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; GCN-LABEL: test_sreg:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_add_u32 s4, s8, s12
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; GCN-NEXT: s_addc_u32 s5, s9, s13
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; GCN-NEXT: s_addc_u32 s6, s10, s14
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; GCN-NEXT: s_addc_u32 s7, s11, s15
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: v_mov_b32_e32 v2, s6
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; GCN-NEXT: v_mov_b32_e32 v3, s7
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; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%result = add i128 %a, %b
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store i128 %result, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() readnone
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