578741b5e8
Currently, we use `AAAMDWavesPerEU` to iteratively update values based on attributes from the associated function, potentially propagating user-annotated values, along with `AAAMDFlatWorkGroupSize`. Similarly, we have `AAAMDFlatWorkGroupSize`. However, since the value calculated through the flat workgroup size always dominates the user annotation (i.e., the attribute), running `AAAMDWavesPerEU` iteratively is unnecessary if no user-annotated value exists. This PR completely rewrites how the `amdgpu-waves-per-eu` attribute is handled in `AMDGPUAttributor`. The key changes are as follows: - `AAAMDFlatWorkGroupSize` remains unchanged. - `AAAMDWavesPerEU` now only propagates user-annotated values. - A new function is added to check and update `amdgpu-waves-per-eu` based on the following rules: - No waves per eu, no flat workgroup size: Assume a flat workgroup size of `1,1024` and compute waves per eu based on this. - No waves per eu, flat workgroup size exists: Use the provided flat workgroup size to compute waves-per-eu. - Waves per eu exists, no flat workgroup size: This is a tricky case. In this PR, we assume a flat workgroup size of `1,1024`, but this can be adjusted if a different approach is preferred. Alternatively, we could directly use the user-annotated value. - Both waves per eu and flat workgroup size exist: If there’s a conflict, the value derived from the flat workgroup size takes precedence over waves per eu. This PR also updates the logic for merging two waves per eu pairs. The current implementation, which uses `clampStateAndIndicateChange` to compute a union, might not be ideal. If we think from ensure proper resource allocation perspective, for instance, if one pair specifies a minimum of 2 waves per eu, and another specifies a minimum of 4, we should guarantee that 4 waves per eu can be supported, as failing to do so could result in excessive resource allocation per wave. A similar principle applies to the upper bound. Thus, the PR uses the following approach for merging two pairs, `lo_a,up_a` and `lo_b,up_b`: `max(lo_a, lo_b), max(up_a, up_b)`. This ensures that resource allocation adheres to the stricter constraints from both inputs. Fix #123092.
266 lines
10 KiB
LLVM
266 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals all --version 4
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; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a -passes=amdgpu-attributor %s | FileCheck %s
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define amdgpu_kernel void @kernel_uses_asm_virtreg() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg(
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; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "a"(i32 poison)
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ret void
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}
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define amdgpu_kernel void @kernel_uses_asm_virtreg_def() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_def(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: [[DEF:%.*]] = call i32 asm sideeffect "
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; CHECK-NEXT: ret void
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;
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%def = call i32 asm sideeffect "; def $0", "=a"()
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ret void
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}
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define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_def_tuple(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: [[DEF:%.*]] = call i64 asm sideeffect "
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; CHECK-NEXT: ret void
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;
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%def = call i64 asm sideeffect "; def $0", "={a[0:1]}"()
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ret void
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}
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define amdgpu_kernel void @kernel_uses_asm_virtreg_second_arg() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_virtreg_second_arg(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "v,a"(i32 poison, i32 poison)
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ret void
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}
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define amdgpu_kernel void @kernel_uses_non_agpr_asm() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_non_agpr_asm(
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; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "v"(i32 poison)
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ret void
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}
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define amdgpu_kernel void @kernel_uses_asm_physreg() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "{a0}"(i32 poison)
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ret void
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}
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define amdgpu_kernel void @kernel_uses_asm_physreg_tuple() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_uses_asm_physreg_tuple(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "{a[0:1]}"(i64 poison)
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ret void
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}
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define void @func_uses_asm_virtreg_agpr() {
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; CHECK-LABEL: define void @func_uses_asm_virtreg_agpr(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "a"(i32 poison)
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ret void
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}
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define void @func_uses_asm_physreg_agpr() {
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; CHECK-LABEL: define void @func_uses_asm_physreg_agpr(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "{a0}"(i32 poison)
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ret void
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}
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define void @func_uses_asm_physreg_agpr_tuple() {
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; CHECK-LABEL: define void @func_uses_asm_physreg_agpr_tuple(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: ret void
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;
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call void asm sideeffect "; use $0", "{a[0:1]}"(i64 poison)
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ret void
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}
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declare void @unknown()
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define amdgpu_kernel void @kernel_calls_extern() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern(
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; CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
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; CHECK-NEXT: call void @unknown()
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; CHECK-NEXT: ret void
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;
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call void @unknown()
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ret void
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}
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define amdgpu_kernel void @kernel_calls_extern_marked_callsite() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern_marked_callsite(
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; CHECK-SAME: ) #[[ATTR3]] {
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; CHECK-NEXT: call void @unknown() #[[ATTR7:[0-9]+]]
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; CHECK-NEXT: ret void
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;
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call void @unknown() #0
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ret void
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}
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define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect(
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; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR3]] {
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; CHECK-NEXT: call void [[INDIRECT]]()
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; CHECK-NEXT: ret void
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;
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call void %indirect()
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ret void
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}
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define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(ptr %indirect) {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(
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; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR3]] {
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; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR7]]
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; CHECK-NEXT: ret void
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;
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call void %indirect() #0
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ret void
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}
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define amdgpu_kernel void @kernel_transitively_uses_agpr_asm() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_transitively_uses_agpr_asm(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void @func_uses_asm_physreg_agpr()
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; CHECK-NEXT: ret void
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;
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call void @func_uses_asm_physreg_agpr()
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ret void
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}
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define void @empty() {
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; CHECK-LABEL: define void @empty(
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; CHECK-SAME: ) #[[ATTR1]] {
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; CHECK-NEXT: ret void
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;
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ret void
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}
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define void @also_empty() {
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; CHECK-LABEL: define void @also_empty(
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; CHECK-SAME: ) #[[ATTR1]] {
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; CHECK-NEXT: ret void
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;
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ret void
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}
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define amdgpu_kernel void @kernel_calls_empty() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_empty(
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; CHECK-SAME: ) #[[ATTR1]] {
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; CHECK-NEXT: call void @empty()
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; CHECK-NEXT: ret void
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;
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call void @empty()
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ret void
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}
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define amdgpu_kernel void @kernel_calls_non_agpr_and_agpr() {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_non_agpr_and_agpr(
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; CHECK-SAME: ) #[[ATTR0]] {
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; CHECK-NEXT: call void @empty()
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; CHECK-NEXT: call void @func_uses_asm_physreg_agpr()
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; CHECK-NEXT: ret void
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;
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call void @empty()
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call void @func_uses_asm_physreg_agpr()
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ret void
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}
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define amdgpu_kernel void @kernel_calls_generic_intrinsic(ptr %ptr0, ptr %ptr1, i64 %size) {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_generic_intrinsic(
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; CHECK-SAME: ptr [[PTR0:%.*]], ptr [[PTR1:%.*]], i64 [[SIZE:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr [[PTR0]], ptr [[PTR1]], i64 [[SIZE]], i1 false)
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; CHECK-NEXT: ret void
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;
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call void @llvm.memcpy.p0.p0.i64(ptr %ptr0, ptr %ptr1, i64 %size, i1 false)
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ret void
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}
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32 immarg, i32 immarg, i32 immarg)
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define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(ptr addrspace(1) %out, float %a, float %b, <32 x float> %c) {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_mfma.f32.32x32x1f32(
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; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]], <32 x float> [[C:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[RESULT:%.*]] = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float [[A]], float [[B]], <32 x float> [[C]], i32 0, i32 0, i32 0)
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; CHECK-NEXT: store <32 x float> [[RESULT]], ptr addrspace(1) [[OUT]], align 128
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; CHECK-NEXT: ret void
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;
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%result = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %a, float %b, <32 x float> %c, i32 0, i32 0, i32 0)
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store <32 x float> %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @kernel_calls_workitem_id_x(ptr addrspace(1) %out) {
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; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_workitem_id_x(
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; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: store i32 [[RESULT]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%result = call i32 @llvm.amdgcn.workitem.id.x()
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) {
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; CHECK-LABEL: define amdgpu_kernel void @indirect_calls_none_agpr(
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; CHECK-SAME: i1 [[COND:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty
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; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]]
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; CHECK: 2:
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; CHECK-NEXT: call void @also_empty()
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; CHECK-NEXT: br label [[TMP6:%.*]]
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; CHECK: 3:
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; CHECK-NEXT: br i1 true, label [[TMP4:%.*]], label [[TMP5:%.*]]
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; CHECK: 4:
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; CHECK-NEXT: call void @empty()
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; CHECK-NEXT: br label [[TMP6]]
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; CHECK: 5:
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; CHECK-NEXT: unreachable
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; CHECK: 6:
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; CHECK-NEXT: ret void
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;
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%fptr = select i1 %cond, ptr @empty, ptr @also_empty
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call void %fptr()
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ret void
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}
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attributes #0 = { "amdgpu-agpr-alloc"="0" }
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;.
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; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR2:[0-9]+]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR3]] = { "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
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; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
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; CHECK: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
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; CHECK: attributes #[[ATTR7]] = { "amdgpu-agpr-alloc"="0" }
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;.
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