fc0653f31c
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.
57 lines
2.0 KiB
LLVM
57 lines
2.0 KiB
LLVM
; RUN: llc -O0 -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_branch:
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; GCNNOOPT: v_writelane_b32
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; GCNNOOPT: v_writelane_b32
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; GCN: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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; GCNNOOPT: v_readlane_b32
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; GCNNOOPT: v_readlane_b32
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; GCN: buffer_store_{{dword|b32}}
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; GCNNOOPT: s_endpgm
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @test_branch(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i32 %val) #0 {
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%cmp = icmp ne i32 %val, 0
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br i1 %cmp, label %store, label %end
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store:
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store i32 222, ptr addrspace(1) %out
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ret void
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end:
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ret void
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}
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; GCN-LABEL: {{^}}test_brcc_i1:
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; GCN: s_load_{{dword|b32}} [[VAL:s[0-9]+]]
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; GCNNOOPT: s_mov_b32 [[ONE:s[0-9]+]], 1{{$}}
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; GCNNOOPT: s_and_b32 s{{[0-9]+}}, [[VAL]], [[ONE]]
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; GCNOPT: s_bitcmp0_b32 [[VAL]], 0
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; GCNNOOPT: s_cmp_eq_u32
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; GCN: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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; GCN: buffer_store_{{dword|b32}}
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define amdgpu_kernel void @test_brcc_i1(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i1 %val) #0 {
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%cmp0 = icmp ne i1 %val, 0
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br i1 %cmp0, label %store, label %end
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store:
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store i32 222, ptr addrspace(1) %out
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ret void
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end:
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ret void
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}
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attributes #0 = { nounwind }
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